MK50H28DIP ST Microelectronics, Inc., MK50H28DIP Datasheet

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MK50H28DIP

Manufacturer Part Number

MK50H28DIP

Description

Multi Logical Link Frame Relay Controller

Manufacturer

ST Microelectronics, Inc.

Datasheet

1.MK50H28DIP.pdf (64 pages)

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SECTION 1 - FEATURES

March 2000

nex D Standards for Frame Relay Service and

Additional Pocedures for Permanent Virtual

Circuits(PVCs).

Processing - all frame data received).

Bi-directional message processing.

in the timing or content of events.

nT2/T392, nN1/N391, nN2/N392, nN3/N393

and dN1 for the LMI/LIV channel.

and Congestion Statistics for all the active

channels.

on DLCI 0 or 1023.

field with a maximum of 8192 active channels

or DLCIs (Data Link Connection Identifiers)

higher rate of service.

- Initialization Block

- Address Look Up Table

- Separate Receive and Transmit Rings of vari-

able size for each active channel

length.

transmission (1-62 flags between frames).

Loopback, Clockless Loopback, and Self Test.

and 16 bit systems; All inputs and outputs are

TTL compatible.

Based on ITU Q.933 Annex A and T1.617 An-

Optional Transparent Mode (no LMI Protocol

Local Management Link Protocol with optional

Detects and indicates service-affecting errors

Programmable Timers/Counters: nT1/T391,

Provides Error Counters for the LMI channel

LMI/LIV Frames can be transmitted/received

Supports reception of up to 4 octets of address

Priority DLCI scheme for channels requiring

Buffer Management includes:

- Context Table

On chip DMA control with programmable burst

Handles all HDLC frame formatting:

Programmable minimum frame spacing on

Selectable FCS (CRC) of 16 or 32 bits.

Testing Facilities: Internal Loopback, Silent

System clock rates up to 25 MHz.

CMOS process; Fully compatible with both 8

Programmable for full or half duplex operation.

- Zero bit insertion and deletion

- FCS (CRC) generation and detection

- Frame delimiting with flags

FRAME RELAY CONTROLLER

SECTION 2 - DESCRIPTION

The STMicroelectronics MK50H28 Multi-Logical

Link Communications Controller is a CMOS VLSI

device which provides link level data communica-

tions control for Frame Relay Applications on Per-

manent Virtual Circuits (PVCs). The MK50H28

will perform frame formating including: frame de-

limiting with flags, transparency (so-called ”bit-

stuffing”), plus FCS (CRC) generation and detec-

tion. It also supports Local Management Interface

(LMI) protocol with the ”Optional Bidirectional Pro-

cedures” (Annex D, T1.617 - 1991 and T1.617a-

1994).

One of the outstanding features of the MK50H28

is its buffer management which includes on-chip

dual channel DMA. This feature allows users to

receive and transmit multiple data frames at a

time. (A conventional serial communications con-

trol chip plus a separate DMA chip would handle

data for only a single block at a time.)

Pin-for-pin compatible and architecturally the

same as the MK50H25 (X.25/LAPD) and

MK50H27 (CCS#7).

MULTI LOGICAL LINK

PLCC52

DIP48

MK50H28

The

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