MK50H28N ST Microelectronics, Inc., MK50H28N Datasheet
MK50H28N
Related parts for MK50H28N
MK50H28N Summary of contents
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SECTION 1 - FEATURES Based on ITU Q.933 Annex A and T1.617 An- nex D Standards for Frame Relay Service and Additional Pocedures for Permanent Virtual Circuits(PVCs). Optional Transparent Mode (no LMI Protocol Processing - all frame data received). ...
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MK50H28 DESCRIPTION (Continued) MK50H28 will move multiple blocks of receive and transmit data directly into and out of memory through the Host’s bus. Moreover, the memory management capability includes the chaining of long frames. A possible system configuration for the ...
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PLCC52 PIN CONNECTION (Top view) DAL02 DAL01 DAL00 READ INTR DALI DALO DAS BMO/BYTE/BUSREL No Connect BM1/BUSAKO HOLD/BUSRQ ALE/ MK50H28Q 20 21 MK50H28 47 46 DAL13 DAL14 DAL15 A16 A17 A18 A19 A20 A21 A22 No ...
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MK50H28 TAble 1 - PIN DESCRIPTION LEGEND: I Input only IO Input / Output OD Open Drain (no internal pull-up) Note: Pin out for 52 pin PLCC is shown in brackets. SIGNAL NAME PIN(S) TYPE DAL<15:00> 2-9 IO/3S 40-47 [2-10 ...
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Table 1: PIN DESCRIPTION (continued) SIGNAL NAME PIN(S) TYPE HOLD 17 IO/OD BUSRQ [19] ALE 18 O/3S AS [20] HLDA 19 [21 [22] ADR 21 [23] READY 22 IO/OD [24] If CSR4<00> BCON = 1, I/O PIN 15 ...
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MK50H28 Table 1: PIN DESCRIPTION (continued) SIGNAL NAME PIN(S) TYPE RESET 23 [25] TCLK 25 [28] DTR 26 IO RTS [29] RCLK 27 [30] SYSCLK 28 [31 [32] DSR 30 IO CTS [33 [34] A<23:16> ...
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Figure 1: Possible System Configuration for the MK50H28 MEMORY (MULTIPLE DATA BLOCKS) HOST PROCESSOR (68000, 80186, Z8000, ETC) 16-BIT DATA BUS INCLUDING 24-BIT ADDRESS AND BUS CONTROL MK50H28 LINE DRIVERS AND RECEIVERS ELECTRICAL I/O (SUCH AS RS-232C, RS-423, RS-422) DATA ...
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MK50H28 Figure 2: MK50H28 Simplified Block Diagram DMA CONTROLLER SYSCLK RCLK RD 8/64 READY READ DAS CONTROL / STATUS REGISTERS INTERNAL BUS RECEIVER TRANSMITTER FIFO FIFO RECEIVER TRANSMITTER LOOPBACK TEST FIRMWARE ROM MICRO TIMERS CONTROLLER VCC VSS ...
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Functional Blocks Refer to the block diagram in Figure 2. The MK50H28 is primarily initialized and control- led through six 16-bit Control and Status Regis- ters (CSR0 thru CSR5). The CSR’s are accessed through two bus addressable ports, the ...
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MK50H28 3.1.7 DMA Controller The MK50H28 has an on-chip DMA Controller cir- cuit. This allows it to access memory without re- quiring host software intervention. Whenever the MK50H28 requires access to the host memory it will negotiate for mastership of ...
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Each entry will consist of two 16-bit words containing the24-bit address of the context table entry (XCTADR or RCTADR) corresponding to the interrupt, a 7-bit field for the descriptor index (CURXD or CURRD) ...
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MK50H28 Figure 3: MK50H28 Memory Management Structure CSR2, CSR3 PTR TO INIT INIT BLOCK MODE TIMER VALUES PTR TO CT PTR TO ALT PTR TO TINT DR PTR TO RINT DR PTR TO STATUS BUFFER LMI ERROR COUNTERS PRIORITY DLCI ...
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Table 1 - MK50H28 Frame Types INFORMATION ELEMENT Message Type STATUS_ENQUIRY STATUS UPDATE_STATUS NOTES: 1. STATUS_ENQUIRY Frame - This Frame has the format as shown in Figure 4. 2. STATUS Frame - This Frame has the format as shown in ...
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MK50H28 STATUS ENQUIRY is received, the device is- sues the LMI Received primitive 13 (with PPARM=1) and expects the host to respond with LMI Status Request Primitive 11 with UPARM=0 (when the host is ready to transmit the Full STATUS ...
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Figure 4: Sample Annex A STATUS_ENQUIRY Frame ...
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MK50H28 Figure 6: Sample Annex D STATUS Frame (Full ...
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SECTION 4 PROGRAMMING SPECIFICATION This section defines the Control and Status Reg- isters and the memory data structures required to program the MK50H28. 4.1 Control and Status Registers There are six Control and Status Registers (CSR’s) resident within the MK50H28. ...
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MK50H28 4.1.1.2 Register Data Port (RDP BIT NAME 15:00 CSR DATA Writing data to the RDP loads data into the CSR selected by RAP. Reading the data from RDP reads the data ...
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BIT NAME 11 TXON TRANSMITTER ON indicates that the transmit ring access is enabled. TXON is set as the Start primitive is issued if the DTX bit is "0" or afterward as DTX is cleared. TXON is cleared upon recognition ...
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MK50H28 4.1.2.2 Control and Status Register 1 (CSR1) RAP <3:1> = 133 BIT NAME 15 UERR USER ...
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BIT NAME 7 Auto LMI: Instructs the device to enter the Auto LMI Mode of operation. Auto LMI with UPARM=0 causes the device to enter User mode of operation. Auto LMI with UPARM=1 causes the device to enter Network mode ...
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MK50H28 BIT NAME 07 PLOST PROVIDER PRIMITIVE LOST is set by the MK50H28 when a provider primitive cannot be issued because the PAV bit is still set from the previous provider primitive. PLOST is cleared when PAV is cleared or ...
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Control and Status Register 2 (CSR2) RAP<3:1> BIT ...
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MK50H28 4.1.2.5 Control and Status Register 4 (CSR4) CSR4 allows redefinition of the bus master interface. RAP<3:1> ...
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BIT NAME 05 BSWPC This bit determines the byte ordering of all "non-data" DMA transfers. This transfers refers to any DMA transfers that access memory other than the data buffers themselves. This includes the Initialization Block, Descriptors, and Status Buffer. ...
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MK50H28 4.1.2.6 Control and Status Register 5 (CSR5) CSR5 facilitates control and monitoring of modem controls. RAP<3:1> BIT NAME 15:06 0 Reserved, must be written as zeroes. 5 XEDGE ...
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Initialization / Priority DLCI Block MK50H28 initialization includes the reading of the Initialization Block in the off-chip memory to obtain the operating parameters. The Initialization Block is defined below. Upon receiving an Init primitive, the first 16 words of ...
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MK50H28 4.2.1 Mode Register The Mode Register allows alteration of the MK50H28’s operating parameters IADR + 00 BIT NAME 15:11 MFS<4:0> Minimum Frame Spacing defines the minimum number of flag sequences transmitted between adjacent frames transmitted by the ...
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BIT NAME 02:00 LBACK Loopback Control puts MK50H28 into one of several loopback configurations. LBACK 4.2.2 Timers/Counters There are 8 independent counter-timers. The lower 8 bits of IADR+08 are used as a scaler for nT1, nT2 and TP. The scaler ...
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MK50H28 TIMER User N392 / Number of errors occuring on the LMI channel before an alarm is declared. In non-Auto nN2 LMI Mode, timer time-outs are ignored and nN2 is only incremented when a STATUS frame is received with bad ...
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Context Table (CT) Address 1 5 IADR + 16 0 IADR + 18 BIT NAME 15:08 0 Reserved, must be written as a zero. 07:00/15:00 CTADR CONTEXT TABLE ADDRESS. The CT Address must begin on a word boundary. 4.2.4 ...
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MK50H28 Figure 8a: Context Table MSB CTADR+ CTADR+02 CTADR+04 CTADR+06 DLCI (HIGH ORDER) CTADR+08 CTADR+ ...
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The contents of each CT entry block are described below: WORD NAME CT+00 TXRDY (15) The host sets this bit only if the channel is ready to transmit. If this bit is not set, the MK50H28 will not transmit data ...
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MK50H28 WORD NAME CT+14 SRIP Shared Receive Descriptro Ring Index Pointer. This field contains the Index Pointer to the CT entry with the CURRD and RDRA (CTADR+14, +16 used for received frames rather than the CURRD & RDRA ...
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Transmit and Receive Interrupt Descriptor Rings The MK50H28 has two descriptor ring structures for the purpose of queuing Transmit and Receive inter- rupts. The pointers to these two descriptor rings are located at IADR+24 through IADR+30. These de- scriptor ...
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MK50H28 4.2.6 Address Lookup Table (ALT) Address IADR + 20 IADR + 22 BIT NAME 15:08 0 Reserved, must be written as a zero. 07:00/15:00 ALTADR ADDRESS LOOKUP TABLE ADDRESS. The ALT Address must begin on a word boundary. 4.2.6a ...
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Status Buffer Address IADR + 40 IADR + 42 BIT NAME 15:08 0 Must be written as zeroe if CSR2<14> bit EIBEN = 0 07:00/15:00 SBA STATUS BUFFER ADDRESS points word status buffer into which status ...
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MK50H28 4.2.9 Priority DLCI Block The Priority DLCI Block (PDB mechanism through which the host can demand the MK50H28 to im- mediately service certain desired DLCIs. The host should first set up entries in the PDB before setting ...
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Receive Message Descriptor Entry 4.3.1.1 Receive Message Descriptor 0 (RMD0) For Non-LMI Channel C BIT NAME 15 OWNA When this bit ...
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MK50H28 4.3.1.2 Receive Message Descriptor 0 (RMD0) For LMI Channel (Contimued) BIT NAME 14 EOR End Of Ring. Setting this bit to 1 indicates that this is the last descriptor in the ring Reserved. Must be written as ...
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Receive Message Descriptor 2 (RMD2 BIT NAME 15:00 BCNT Buffer Byte Count is the length of the buffer pointed to by this descriptor expressed in two’s complement. This field is written to by ...
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MK50H28 BIT NAME 15 OWNA When this bit is a zero, the HOST owns this descriptor. When this bit is a one the MK50H28 owns this descriptor. The host sets the OWNA bit after filling the buffer pointed to by ...
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BIT NAME 11:09 LMI Frame These bits define the type of frame to be transmitted when transmission occurs due to Type to be LMI polling (enabled by UPRIM 8 with UPARM=2 - see 4.1.2.2). Transmitted 11:09 0 Reserved. Must be ...
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MK50H28 4.3.2.5 Transmit Message Descriptor 3 (TMD3 BIT NAME 15:00 MCNT Message byte count is the length, in octets, of the data contained in the corresponding buffer. The value of this field is expressed ...
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FIELD PART NUMBER Indicates the part number (28 Hex) for the MK50H28. REV INDICATOR Indicates the current revision of the part. PHASE Indicates the current phase of operation. XCTADR:<23:00> Current Transmit Context Table Address. This pointer indicates the address of ...
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MK50H28 4.4.2.1 User Mode (Auto LMI Mode) - Continued In User Mode the MK50H28 will perform the following functions: 1. Transmit STATUS ENQUIRY frames at an interval determined by the nT1 timer. 2. After every nN1 transmissions of STATUS ENQUIRY ...
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Bi-directional Procedures (Auto LMI Mode) - Continued 3. After every nN1/N391 transmissions of STATUS ENQUIRY with Report Type of "LIV Only", the MK50H28 transmits a STATUS ENQUIRY with Report Type of "Full Status" received Full STATUS frame ...
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MK50H28 4.4.5 Receiving LMI Frames The following procedure should be performed to receive the LMI frames: 1. Whenever a LMI frame is received the MK50H28 issues a PPRIM of 13. In response to that the host may look at the ...
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Disabling the MK50H28 The following procedure should be followed to disable the MK50H28: 1. Issue the STOP primitive through CSR1. This will disable the MK50H28 from receiving or trans- mitting. The TD pin will be held high while the ...
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MK50H28 ABSOLUTE MAXIMUM RATINGS Symbol T Temperature Under Bias UB T Storage Temperature stg V Voltage on any pin with respect to ground G P Power Dissipation tot Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage ...
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AC TIMING SPECIFICATIONS CONTINUED percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high time RCH 15 RCLK ...
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MK50H28 AC TIMING SPECIFICATIONS CONTINUED percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 DALO T DALO ...
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Figure 9a: TTL Output Load Diagram TEST POINT FROM OUTPUT UNDER TEST C L NOTE: This load is used on all outputs except INTR, HOLD, READY. Figure 10: MK50H28 Serial Link Timing Diagram RCLK RD TCLK TD TIMING MEASUREMENTS ARE ...
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MK50H28 Figure 11: MK50H28 BUS Master Timing (Read) (for CYCLE = 0, CSR2<15>) SYSCLK 64 HOLD 24 HLDA A 16-23 ALE DAS READY DAL0-15 DALO DALI READ BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and T5 will be removed ...
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Figure 11a: MK50H28 Reduced Cycle BUS Master Timing (Read) (for CYCLE = 1, CSR2<15>) SYSCLK 64 HOLD HLDA A 16-23 ALE DAS READY DAL0-15 DALO DALI READ BM0,1 NOTES: 1. This reduced DMA Cycle Time is selected by setting CSR2 ...
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MK50H28 Figure 12: MK50H28 BUS Master Timing Diagram (Write) (for CYCLE = 0, CSR2<15>) SYSCLK 64 HOLD 24 HLDA A 16-23 ALE DAS READY DAL0-15 DALO DALI READ BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and T5 will be ...
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Figure 12a: MK50H28 Reduced Cycle BUS Master Timing (Write) (for CYCLE = 1, CSR2<15>) SYSCLK HOLD HLDA A 16-23 ALE DAS READY DAL0-15 DALO DALI READ BM0,1 NOTES: 1. This Reduced DMA Cycle Time is selected by setting CSR2 bit ...
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MK50H28 Figure 12b: BUS Master BURST Timing (Reduced Cycle - Write SYSCLK 64 HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY 29 DAL0-15 DALO 45 DALI READ BM0,1 58/ ...
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Figure 13: MK50H28 BUS Slave Timing Diagram (Read) SYSCLK CS ADR DAS READY READ (Read) DAL 0-15 NOTES: 1. Input setup and hold times are in minimum values required to or from the particular edge specified in order to be ...
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MK50H28 Figure 14: MK50H28 BUS Slave Timing Diagram (Write) SYSCLK CS ADR DAS READY READ (Write) DAL0-15 NOTES: 1. Input setup and hold times are the minimum values required to or from the particular edge specified in order to be ...
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ORDERING INFORMATION: MK50H28 PACKAGE N = Plastic DIP (48 Pins Plastic J-Leaded Chip Carrier (52 Pins) PART # 50H28 = Frame Relay REVISION CODE (Contact factory representative for current revision) SPEED SORT (25 = ...
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MK50H28 mm DIM. MIN. TYP. MAX. a1 0.63 b 0.45 b1 0.23 0.31 0.009 b2 1.27 D 62.74 E 15.2 16.68 e 2.54 e3 58.42 F 14.1 I 4.445 L 3.3 62/64 inch MIN. TYP. MAX. 0.025 0.018 0.012 0.050 ...
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DIM. MIN. TYP. MAX. MIN. A 4.20 5.08 A1 0.51 A3 2.29 3.30 B 0.33 0.53 B1 0.66 0.81 C 0.25 0.01 D 19.94 20.19 D1 19.05 19.20 D2 17.53 18.54 D3 15.24 0.60 E 19.94 20.19 E1 19.05 ...
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MK50H28 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...