SI4133 ETC, SI4133 Datasheet
SI4133
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SI4133 Summary of contents
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... Digital Cellular Telephones GSM, DCS1800, PCS1900 Description The Si4133 is a monolithic integrated circuit that performs both IF and dual- band RF synthesis for wireless communications applications. The Si4133 includes three VCOs, loop filters, reference and VCO dividers, and phase detectors. Divider and power-down settings are programmable through a three-wire serial interface ...
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Rev. 1.1 ...
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... Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 PLL Loop Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RF and IF Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Reference Frequency Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Auxiliary Output (AUXOUT Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Pin Descriptions: Si4133- Pin Descriptions: Si4133- Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Si4133 Derivative Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Package Outline: Si4133- Package Outline: Si4133- Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Rev. 1.1 Si4133 Page 3 ...
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Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature Supply Voltage Supply Voltages Difference Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply ...
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... –500 µ 500 µ Rev. 1.1 Si4133 Min Typ Max Unit — — — — — 1 — µA 0.7 V — — — — 0 – ...
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Table 4. Serial Interface Timing (V = 2 –40 to 85° Parameter SCLK Cycle Time SCLK Rise Time SCLK Fall Time SCLK High Time SCLK Low Time 2 ...
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... Figure 3. Serial Word Format t hold D16 D15 data addres s field Rev. 1.1 Si4133 en3 t en2 t w Las t bit c loc ked field 7 ...
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... RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted. 2. Extended frequency operation only. V RFLB pins. See Application Note 41 for more details on the Si4133 extended frequency operation. 3. From power up request (PWDNB or SENB during a write bits PDIB and PDRB in Register and IF synthesizers ready (settled to within 0 ...
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... RF1 = 1.6 GHz, RF2 = 1.2 GHz, IFOUT = 550 MHz, LPWR = 0, for all parameters unless otherwise noted. 2. Extended frequency operation only. V RFLB pins. See Application Note 41 for more details on the Si4133 extended frequency operation. 3. From power up request (PWDNB or SENB during a write bits PDIB and PDRB in Register and IF synthesizers ready (settled to within 0 ...
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and IF sy nthes iz ers settled to w ithin 0.1 ppm f requency error. t pup ...
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... TRACE A: Ch1 FM Main Time A Marker 1.424 kHz Real 160 Hz /div 176 Hz Start Figure 6. Typical Transient Response RF1 at 1.6 GHz with 200 kHz Phase Detector Update Frequency Rev. 1.1 us 174.04471 711.00 Stop: 399.6003996 us Si4133 Hz 11 ...
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−60 −70 −80 −90 −100 −110 −120 −130 −140 2 10 Figure 7. Typical RF1 Phase Noise at 1.6 GHz with 200 kHz Phase Detector Update Frequency Figure 8. Typical RF1 Spurious Response at 1.6 GHz ...
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... Offset Frequency (Hz) Figure 9. Typical RF2 Phase Noise at 1.2 GHz with 200 kHz Phase Detector Update Frequency Figure 10. Typical RF2 Spurious Response at 1.2 GHz with 200 kHz Phase Detector Update Frequency Rev. 1 Si4133 13 ...
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−70 −80 −90 −100 −110 −120 −130 −140 −150 2 10 Figure 11. Typical IF Phase Noise at 550 MHz with 200 kHz Phase Detector Update Frequency Figure 12. IF Spurious Response at 550 MHz with ...
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... 0.022 rie ing IF ou tpu t divid lue Figure 13. Typical Application Circuit: Si4133- tro lle ...
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... IF output frequencies, if needed. The divider is programmable, capable of dividing The unique PLL architecture used in the Si4133 produces settling (lock) times that are comparable in speed to fractional-N architectures without suffering the high phase noise or spurious modulation effects often ...
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... An external inductance of 1.8 nH should be connected between RFLC and RFLD as shown in Figure 15. This, in addition to 2 package inductance, will present the correct manufacturing, the external inductance can vary ±10% of its nominal value and the Si4133 will correct for the L Range EXT variation with the self-tuning algorithm. (nH) ...
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... The settling time for the PLL is directly proportional to its phase detector update period T (T equals 1 typical transient response is shown in Figure 6 on page Only the 11. During the first 13 update periods the Si4133 executes the self-tuning algorithm. Thereafter the PLL Rev. 1.1 /R) and REF Relative P ...
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... When the PWDNB pin is high, power management is under control of the Power Down register bits. load. See The IF and RF sections of the Si4133 circuitry can be can be individually powered down by setting the Power Down MATCH register bits PDIB and PDRB low, respectively. Note that the reference frequency amplifier will also be powered up if either the PDRB and PDIB bits are high ...
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Auxiliary Output (AUXOUT) The signal appearing on AUXOUT is selected by setting the AUXSEL bits in the Main Configuration register (Register 0). PWDNB Pin AUTOPDB PWDNB = 0 PWDNB = 1 450 400 350 LPWR=0 300 ...
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... AUXSEL IFDIV [1:0] [1: [17:0] RF1 N [16:0] RF2 Rev. 1.1 Si4133 Bit Bit Bit Bit Bit Bit LPWR 0 AUTO AUTO RF PDB K PWR [1:0] [1: PDIB ...
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Register 0. Main Configuration Address Field = A[3:0] = 0000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name AUXSEL Bit Name 17:14 Reserved 13:12 AUXSEL [1:0] 11:10 IFDIV [1:0] ...
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... RF2 Phase Detector Gain Constant.* N Value K P2 <4096 = 00 4096–8191 = 01 8192–16383 = 10 >16383 = 11 RF1 Phase Detector Gain Constant.* N Value K P1 <8192 = 00 8192–16383 = 01 16384–32767 = 10 >32767 = 11 Rev. 1.1 Si4133 [1:0] [1:0] [1: use these recommended values P 23 ...
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Register 2. Power Down Address Field (A[3:0]) = 0010 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:2 Reserved 1 PDIB 0 PDRB Note: Enabling any ...
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... 8189 8189 8189 Function can be any value from 7 to 8189 8189 8189 8189 if K Rev. 1.1 Si4133 Function ...
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Register 8. IF R-Divider Address Field (A[3:0]) = 1000 Bit D17 D16 D15 D14 D13 D12 D11 D10 D9 Name Bit Name 17:13 Reserved Program to zero. 12:0 R R-Divider for ...
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... Pin Descriptions: Si4133-BT SDA TA GNDR GNDR GNDR GNDR RFOUT V DDR Pin Number(s) Name Description 1 SCLK Serial clock input 2 SDATA Serial data input GNDR Common ground for RF analog circuitry 4, 5 RFLC, RFLD Pins for inductor connection to RF2 VCO 7, 8 RFLA, RFLB ...
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... Table 13. Pin Descriptions for Si4133 Derivatives—TSSOP Pin Number Si4133 1 SCLK 2 SDATA 3 GNDR 4 RFLD 5 RFLC 6 GNDR GNDR 10 GNDR 11 RFOUT 12 VDDR 13 AUXOUT 14 PWDNB 15 16 GNDD 17 VDDD 18 GNDD IFOUT 23 24 SENB 28 Si4123 Si4122 SCLK SCLK SDATA SDATA GNDR ...
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... Pin Descriptions: Si4133-BM GNDR RFLD RFLC GNDR RFLB RFLA GNDR Pin Number(s) Name Description 1, 4, 7-9, 28 GNDR Common ground for RF analog circuitry 2, 3 RFLC, RFLD Pins for inductor connection to RF2 VCO 5,6 RFLA, RFLB Pins for inductor connection to RF1 VCO 10 RFOUT Radio frequency (RF) output of the selected RF VCO ...
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... Table 14. Pin Descriptions for Si4133 Derivatives—MLP Pin Number Si4133 Si4123 Si4122 GNDR GNDR GNDR RFLD GNDR RFLD RFLC GNDR RFLC GNDR GNDR GNDR RFLB ...
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... Si4112-BM Si4112-BT Si4133 Derivative Devices The Si4133 performs both IF and dual-band RF frequency synthesis. The Si4112, Si4113, Si4122, and the Si4123 are derivatives of this device. Table 15 outlines which synthesizers each derivative device features as well as which pins and registers coincide with each synthesizer. ...
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... Package Outline: Si4133- Figure 19. 24-pin Thin Small Shrink Outline Package (TSSOP) Table 16. Package Diagram Dimensions Symbol Millimeters Min Nom Max A — 1.10 1.20 A1 0.05 — 0.15 A2 0.80 1.00 1.05 b 0.19 — 0.30 c 0.09 — 0.20 D 7.70 7.80 7.90 e 0.65 BSC E 6.40 BSC E1 4.30 4.40 4.50 L 0.45 0.60 0.75 L1 1.00 REF R 0.09 — R1 0.09 — S 0.20 — ...
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... Package Outline: Si4133-BM Figure 20. 28-Pin Micro Leadframe Package (MLP) Table 17. Package Dimensions Controlling Dimension: mm Symbol Millimeters Min Nom A — 0.90 A1 0.00 0.01 b 0.18 0.23 D 5.00 BSC D1 4.75 BSC E 5.00 BSC E1 4.75 BSC 0.50 BSC L 0.50 0.60 Rev. 1.1 Si4133 Max 1.00 0.05 0.30 0.75 ° ...
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Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, Texas 78735 Tel:1+ (512) 416-8500 Fax:1+ (512) 416-9669 Toll Free: 1+ (877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate ...