hpmx-2003 ETC-unknow, hpmx-2003 Datasheet - Page 3

• Manufacturer Part Number: hpmx-2003
• Description: Silicon Bipolar Rfic Vector Modulator
• Manufacturer: ETC-unknow

HPMX-2003 Pin
Description
V
These two pins provide DC power
to the mixers in the RFIC, and are
connected together internal to the
package. They should be con-
nected to a 5 V supply, with appro-
priate AC bypassing (1000 pF typ.)
used near the pins, as shown in
figures 1 and 2. The voltage on
these pins should always be
kept at least 0.8 V more posi-
tive than the DC level on any
of pins 5, 6, 11, or 12. Failure to
do so may result in the modulator
drawing sufficient current
through the data or reference
inputs to damage the IC.
Ground (pins 3, 4, 10, 13 & 14)
These pins should connect with
minimal inductance to a solid
ground plane (usually the back-
side of the PC board). Recom-
mended assembly employs
multiple plated through via holes
where these leads contact the PC
board.
I
I (pin 11) and Q (pin 6) Inputs
The I and Q inputs are designed
for unbalanced operation but can
be driven differentially with simi-
Figure 1. HPMX-2003 Connections Showing Unbalanced LO
and I, Q Inputs.
LO
ref
CC
in
(pin 12) and Q
(pins 1,2)
Q mod
1000 pF
1000 pF
1000 pF
Q ref
+5 V
ref
1
(pin 5),
2
3
4
6
5
7
8
1000 pF
13
16
15
14
12
10
11
9
lar performance. The recom-
mended level of unbalanced I and
Q signals is 2.5 V
age level of 2.5 V above ground.
The reference pins should be DC
biased to this average data signal
level (V
single ended drive, pins 5 and 12
can be tied together. For balanced
operation, 2.5 V
applied across the I
Q
of all four signals should be about
2.5 V above ground. The imped-
ance between any I or Q and
ground is typically 10 K
impedance between I
Q
The input bandwidth typically
exceeds 40 MHz. It is possible to
reduce LO leakage through the IC
by applying slight DC imbalances
between I
and Q
“HPMX-2003 Using Offsets to Im-
prove Lo Leakage”). All perfor-
mance data shown on this data
sheet was taken with unbalanced
I/Q inputs.
LO Input (pins 7 and 8)
The LO input of the HPMX-2003 is
balanced and matched to 50 For
drive from an unbalanced LO, pin
7 should be AC coupled to the LO
DO NOT CONNECT
OPTIONAL INDUCTOR
mod
mod
/Q
and Q
ref
ref
CC
I mod
I ref
(see section entitled
/2 or 2.5 V typ.). For
pairs. The average level
mod
ref
RF out
and I
is typically 10 K .
7-40
p-p
p-p
ref
signals may be
LO
LO
mod
with an aver-
and/or Q
mod
in +
in –
Figure 2. HPMX-2003 Connections Showing Balanced LO
and I, Q Inputs.
/I
ref
and I
Q mod
1000 pF
1000 pF
1000 pF
and the
and the
Q ref
ref
mod
or
+5 V
using a 50
a blocking capacitor (1000 pF
typ.), and pin 8 should be AC
grounded (1000 pF capacitor
typ.), as shown in figure 1. For
drive from a balanced LO source,
50
ing capacitors (1000 pF typ.) are
used on both pins 7 and 8, as
shown in figure 2. The internal
phase shifter allows operation
from 800 - 1000 MHz. The recom-
mended LO input level is -12 dBm.
All performance data shown on
this data sheet was taken with un-
balanced LO operation.
RF Output (pin15)
The RF output of the HPMX-2003
is configured for unbalanced
operation. The output is internally
DC blocked and matched to 50 ,
so a simple 50
all that is required to connect the
modulator to other circuits.
V
Pin 16 is the V
put stage of the IC. It is not inter-
nally connected to the other V
pins. The external connection al-
lows the addition of a small induc-
tor (0 - 6 nH) to tune the output
for minimum VSWR, depending
upon the operating frequency.
CCL
(pin 16)
transmission lines and block-
1
2
3
4
6
5
7
8
1000 pF
transmission line and
16
15
14
13
12
10
11
CC
9
input for the out-
microstrip line is
DO NOT CONNECT
OPTIONAL INDUCTOR
I mod
I ref
RF out
CC