ch7009a ETC-unknow, ch7009a Datasheet
ch7009a
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ch7009a Summary of contents
Page 1
... VGA CRT with the input data. DVI Encode Scaling 3 Scan Conv 24 Flicker Filt 24 Figure 1: Functional Block Diagram *TMDS is Trademark of Silicon Image Inc. CH7009A TM link (DFP can also be TM and RGB bypass mode which DVI (TMDS TM link) PLL 2 DVI DVI 2 Serialize Driver 2 2 ...
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... V 5 DGND 6 7 GPIO[1] / TLDET* GPIO[0] 8 HPDET DGND 12 DVDD RESET AGND 2 Chrontel CH7009 Figure 2: 64-Pin LQFP CH7009A SYNC 48 BCO 47 46 P-Out/TLDET* DVDDV 45 44 AVDD FIN 41 AGND 40 GND 39 CVBS / CVBS 35 ...
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... Address Select (Internal pull-up) This pin determines the IIC address of the device (1,1,1,0,1,AS*,AS). RESET* Reset * Input (Internal pull-up) When this pin is low, the device is held in the power-on reset condition. When this pin is high, reset is controlled through the IIC register. CH7009A The amplitude will ...
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... XO. However, an external clock can drive the XI/FIN input. XO Crystal Output A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached between this pin and XI / FIN. However external CMOS clock is attached to XI/FIN, XO should be left open. CH7009A 201-0000-035 Rev 1.1, 5/8/2000 ...
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... MCP bit. DVDD Digital Supply Voltage DGND Digital Ground DVDDV I/O Supply Voltage TVDD DVI Transmitter Supply Voltage TGND DVI Transmitter Ground AVDD PLL Supply Voltage AGND PLL Ground VDD DAC Supply Voltage GND DAC Ground CH7009A The (3.3V) (3.3V to 1.1V) (3.3V) (3.3V) (3.3V) 5 ...
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... These DVD compatible modes are input in a non-interlaced RGB data format 2 30Hz in progressive scan modes, 60Hz in interlaced modes 6 Refresh Rate XCLK DVI (Hz) Frequency Frequency (MHz) (MHz) <85 <35.5 <355 <85 <31.5 <315 <85 <36 <360 59.94 27 270 50 27 270 <85 <57 <570 <85 <95 <950 <60 <67 <670 <85 <158 <1580 <60 <165 <1650 2 <140 <1400 <30 CH7009A 201-0000-035 Rev 1.1, 5/8/2000 ...
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... BCO 201-0000-035 Rev 1.1, 5/8/2000 TM DVI (TMDS link) PLL DVI DVI Encode Serialize 24 3 PLL3 Timing Scaling TV 3 Scan Conv Encode 24 Flicker Filt 24 Figure 3: DVI Output CH7009A TLC,TLC* 2 TDC0,TDC0* DVI 2 TDC1,TDC1* Driver 2 TDC2,TDC2* 2 VSWING HPDET GPIO[1: IIC SC Control SD RESET* C/H SYNC ISET ...
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... These DVD modes operate with interlaced input, scan conversion and flicker filter are bypassed 2 These DVD modes operate with non-interlaced input, scan conversion is not bypassed 8 TV Output Stan- Scaling Ratios Ratio dard 1:1 PAL 5/4, 1/1 1:1 NTSC 5/4, 1/1 PAL 5/4, 1/1 NTSC 5/4, 1/1 1:1 PAL 5/4, 1/1 1:1 NTSC 5/4, 1/1, 7/8 1:1 PAL 5/4, 1/1, 5/6 1:1 NTSC 1/1, 7/8, 5/6 9:8 NTSC 9:8 NTSC 1/1, 7/8, 5/6 15:12 PAL 15:12 PAL 1/1, 5/6, 5/7 1:1 PAL 1/1, 5/6, 5/7 1:1 NTSC 3/4, 7/10, 5/8 1:1 PAL 5/7, 5/8, 5/9 1:1 NTSC 5/8, 5/9, 1/2 CH7009A 1/1 1/1 201-0000-035 Rev 1.1, 5/8/2000 ...
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... P-OUT / TLDET* BCO 201-0000-035 Rev 1.1, 5/8/2000 DVI (TMDS DVI DVI Encode Serialize 24 3 PLL3 Timing Scaling TV 3 Scan Conv Encode 24 Flicker Filt 24 Figure 4: TV Output Modes CH7009A TM link) PLL TLC,TLC* 2 TDC0,TDC0* DVI 2 TDC1,TDC1* Driver 2 TDC2,TDC2* 2 VSWING HPDET GPIO[1: IIC SC Control ...
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... XCLK = XCLK* to D[11:0 & DE Delay (hold time) t2 DVDDV Digital I/O Supply Voltage 1 D[11:0 times measured when input equals Vref+100mV on rising edges, Vref-100mV on falling edges P-OUT 1 VGA Line Figure 5: Interface Timing CH7009A t1 t2 Min Max Unit DVDDV - 0.2 DVDDV + 0.2 V -0.2 0.2 V TBD ...
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... Y1 byte refers to the next luminance sample, per CCIR-656 standards (the clock frequency is dependent upon the current mode, and is not 27MHz as specified in CCIR-656). All non-active pixels should RGB formats, and 16 for Y and 128 for CrCb in YCrCb formats. 201-0000-035 Rev 1.1, 5/8/2000 CH7009A 11 ...
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... Data) P[7:0] (Blue Data) Figure 6: Multiplexed Input Data Formats (IDF = SAV P0a P0b P0b[11:4] P0b[3:0], P0a[11:8] P0b[11:7], P0b[3:1] P0b[6:4], P0a[11:9], P0b[0], P0a[3] P0a[8:4], P0a[2:0] CH7009A P1a P1b P2a P2b P1b[11:4] P2b[11:4] P2b[3:0], P1b[3:0], P1a[11:8] P2a[11:8] P0a[7:0] P1a[7:0] P2a[7:0] P2b[11:7] P1b[11:7], P1b[3:1] ...
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... CRA (internal signal) P[23:16] (Y Data) P[15:8] (CrCb Data) P[7:0] (ignored) Figure 7: Multiplexed Input Data Formats (IDF = 201-0000-035 Rev 1.1, 5/8/2000 SAV P0a P0b P0b[6:4], P0a[11:9] P0b[5:4], P0a[11:9] CH7009A P1a P1b P2a P2b P0b[11:7] P1b[11:7] P2b[11:7] P2b[6:4], P1b[6:4], P1a[11:9] P2a[11:9] P0a[8:4] P1a[8:4] P2a[8:4] P0b[10:6] P1b[10:6] ...
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... RGB 5-6-5 P0b P1a P1b P0a R0[7] G1[4] R1[7] G0[5] R0[6] G1[3] R1[6] G0[4] R0[5] G1[2] R1[5] G0[3] R0[4] B1[7] R1[4] B0[7] R0[3] B1[6] R1[3] B0[6] G0[7] B1[5] G1[7] B0[5] G0[6] B1[4] G1[6] B0[4] G0[5] B1[3] G1[5] B0[3] 4 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7009A 1 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 3 RGB 5-5-5 P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] P2b P3a P3b Y2[7] ...
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... HPIR (Hot Plug Interrupt Reset) bit in register 1Eh high. The driver should then set the HPIR bit low. 201-0000-035 Rev 1.1, 5/8/2000 4 YCrCb 8-bit P0b P1a P1b P2a 00 00 S[7] Cb2[ S[6] Cb2[ S[5] Cb2[ S[4] Cb2[ S[3] Cb2[ S[2] Cb2[ S[1] Cb2[ S[0] Cb2[0] CH7009A P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] 15 ...
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... Select output signal for BCO pin BCOP BCO polarity GPIOL[1:0] Read or write level for GPIO pins GOENB[1:0] Direction control for GPIO pins SYNCO[1:0] Enables/selects sync output for Scart and bypass modes DACG[1:0] DAC gain control DACBP DAC bypass XOSC[2:0] Crystal oscillator adjustments 16 CH7009A 201-0000-035 Rev 1.1, 5/8/2000 ...
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... CIV[25:0] Calculated sub-carrier increment value read out CIVPN Select PAL-N when in a CIV mode MEM[2:0] Memory sense amp reference adjust VBID Vertical blanking interval defeat PLLCPI TV-Out PLL charge pump current control PLLCAP TV-Out PLL capacitor control 201-0000-035 Rev 1.1, 5/8/2000 CH7009A 17 ...
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... and C, the total capacitance pF) P for the HIGH level, this input current limits the maximum value (where and I DD input P CH7009A +DVDD R P DATAN2 OUT SCLK DATA IN2 IN2 SLAVE ) input input 201-0000-035 Rev 1 ...
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... CH7009 at the register location specified by the address AR[6:0]. Register Address Byte (RAB AR[6] AR[5] 201-0000-035 Rev 1.1, 5/8/2000 ACK Data ACK 1 CH7009 CH7009 acknowledge acknowledge AR[4] AR[3] CH7009A Alternating mode Stop Data n ACK CH7009 Condition acknowledge R AR[2] AR[1] AR[0] 19 ...
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... Master Start Condition Figure 10: Acknowledge on the Bus CH7009 CH7009 acknowledge acknowledge RAB ACK Data ACK Figure 11: Alternating Write Cycles CH7009A not acknowledge acknowledge clock pulse for acknowledgment CH7009 CH7009 acknowledge acknowledge Stop RAB ACK ...
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... DAB, must be produced by the master before each of the RAB, and before each of the data read events. Two consecutive alternating read cycles are shown in Figure 13. 201-0000-035 Rev 1.1, 5/8/2000 CH7009 acknowledge RAB n ACK Data n CH7009A CH7009 CH7009 acknowledge acknowledge ACK Data n+1 ACK Condition ...
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... ACK Restart Device ID Condition Figure 13: Alternating Read Cycle CH7009 CH7009 acknowledge acknowledge ACK Restart Device ID R/W* Condition CH7009A CH7009 acknowledge Master does not acknowledge R/W* ACK Data 1 ACK Restart Condition Master does not acknowledge ...
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... TPVCO4 TPVCO3 DVID0 DVII TPVT5 TPVT4 TPVT3 TPLPF1 TPLPF0 TPVCO8 ResetIB ResetDB TV DACPD3 DACPD2 VID5 VID4 VID3 DID5 DID4 DID3 CH7009A Bit 2 Bit 1 Bit 0 SR2 SR1 SR0 YFFT0 YFFNT1 YFFNT0 YSV0 YCV1 YCV0 TE2 TE1 TE0 SAV2 SAV1 SAV0 HP2 HP1 ...
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... PAL 1024x768 1400x1000 PAL 1024x768 1400x1125 PAL 1024x768 1160x840 NTSC 1024x768 1160x945 NTSC 1024x768 1168x1050 NTSC 720x576 864x625 PAL 720x480 858x525 NTSC CH7009A Symbol: DM Address: 00h Bits SR2 SR1 R/W R/W R can be supported C Scaling Percent Pixel Clock Overscan ...
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... Rev 1.1, 5/8/2000 01 10 NTSC PAL CFF1 CFF0 YFFT1 R/W R/W R CH7009A 11 NTSC-J Symbol: FF Address: 01h Bits YFFT0 YFFNT1 YFFNT0 R/W R/W R ...
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... CH7009A Symbol: VBW Address: 02h Bits YSV0 YCV1 YCV0 R/W R 3.540 5.880 4.430 7.350 3 ...
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... SAV8 HP8 VP8 R/W R/W R CH7009A 6.300 10.400 4.910 8.140 5.380 8.920 5.890 9.770 4.590 7.620 5.250 8.710 5.910 9.790 4.380 7.260 4.930 8.170 5.510 9.140 4.050 6.720 2.660 4 ...
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... SAV5 SAV4 SAV3 R/W R/W R HP5 HP4 HP3 R/W R/W R VP5 VP4 VP3 R/W R/W R CH7009A Symbol: SAV Address: 04h Bits SAV2 SAV1 SAV0 R/W R Symbol: HP Address: 05h Bits HP2 HP1 R/W R Symbol: VP Address: ...
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... Figure 15: Contrast Enhancement diagram 201-0000-035 Rev 1.1, 5/8/2000 BL5 BL4 BL3 R/W R/W R 104 172 240 Yin n CH7009A Symbol: BL Address: 07h Bits BL2 BL1 R/W R Symbol: CE Address: 08h Bits CE2 CE1 R/W ...
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... IBI N9 R/W R/W R Mode PLLCAP Value CH7009A Symbol: TPC Address: 09h Bits PLLCPI PLLCAP R/W R 201-0000-035 Rev 1.1, 5/8/2000 0 R/W 0 ...
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... PAL, 5 1024x768, PAL, 5 1024x768, PAL, 5 1024x768, NTSC, 5 1024x768, NTSC, 5 1024x768, NTSC, 1 720x576, PAL, 1 720x480, NTSC, 1:1 63 CH7009A Symbol: PLLM Address: 0Ah Bits R/W R Symbol: PLLN Address: 0Bh Bits ...
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... CH7009A Symbol: FSCI Address: 0Ch – 0Fh Bits: 8 each FSCI# FSCI# FSCI# R/W R/W PAL-M “Normal Dot Crawl” 762,524,467 622,468,953 573,798,541 ...
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... Dot Crawl” 651,209,077 520,967,262 486,236,111 379,871,962 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 558,179,209 455,846,354 390,725,446 521,519,134 427,355,957 366,305,106 502,361,288 439,566,127 390,725,446 569,807,942 CIV25 CIV24 CIVC1 R/W R/W R CH7009A Symbol: CIVC Address: 10h Bits CIVC0 PALN CIVEN R ...
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... TV PLL’s operating frequency. In slave mode (M/S* = ‘0’) the XCLK input is used as a reference to the TV PLL. The M and N TV PLL divider values are forced to one CIV# CIV# CIV# R/W R/W R M/S* R/W CH7009A Symbol: CIV Address: 11h – 13h Bits: 8 each CIV# CIV# CIV# R/W R Symbol: ...
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... Bits 7-6 of register GPIO control the direction of the GPIO pins. A value of ‘1’ sets the corresponding GPIO pin to an input, and a value of ‘0’ sets the corresponding pin to an output. 201-0000-035 Rev 1.1, 5/8/2000 R/W R/W R HPIR R/W R/W R CH7009A Symbol: IC Address: 1Dh Bits XCMD0 R/W R Symbol: GPIO Address: 1Eh Bits: 8 ...
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... TV. Again, a “0” indicates a valid connection, a “1” indicates an unconnected output SYO VSP HSP R/W R/W R DVIT DACT3 DACT2 CH7009A Symbol: IDF Address: 1Fh Bits IDF2 IDF1 IDF0 R/W R Symbol: CD Address: 20h Bits ...
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... C/H Sync Output 00 No Output 01 VGA Horizontal Sync 10 TV Composite Sync 11 TV Horizontal Sync Bits 7-6 of register DC controls the crystal oscillator. The default value is recommended. 201-0000-035 Rev 1.1, 5/8/2000 SYNCO1 SYNCO0 R/W R CH7009A Symbol: DC Address: 21h Bits DACG1 DACG0 DACBP R/W R ...
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... Buffered Clock Output 100 (for test use only) 101 (for test use only) 110 VGA Vertical Sync 111 TV Vertical Sync TPPD 1 TPPD 0 CTL3 R/W R/W R CH7009A Symbol: BCO Address: 22h Bits BCO2 BCO1 BCO0 R/W R Symbol: TCTL Address: 31h ...
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... Bits 7-6 of register TPVT are reserved bits, and should be left at the default value. 201-0000-035 Rev 1.1, 5/8/2000 R/W R/W R DVID0 DVII Reserved Reserved R/W R/W R TPVT5 TPVT4 TPVT3 R/W R/W R CH7009A Symbol: TVCO Address: 32h Bits TPVCO0 R/W R Symbol: TPCP Address: 33h Bits TPCP1 TPCP0 R/W R Symbol: TPVT ...
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... Color Bars 1X Horizontal Luminance Ramp TPLPF1 TPLPF0 Reserved Reserved Reserved R/W R/W R R/W R/W R ResetIB ResetDB R/W R/W 1 CH7009A Symbol: TPF Address: 36h Bits Reserved R/W R Symbol: TVCOO Address: 37h Bits Reserved R/W R Symbol: TSTP ...
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... DVIP = 1 & FPD = 0 DVIL = 1 & FPD = & FPD = 0 DACPD3 = 0 & FPD = 0 DACPD2 = 0 & FPD = 0 DACPD1 = 0 & FPD = 0 DACPD0 = 0 & FPD = 0 FPD = VID5 VID4 VID3 CH7009A Symbol: PM Address: 49h Bits R/W R Symbol: VID Address: 4Ah Bits: ...
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... DID7 DID6 TYPE: R DEFAULT: 0 Register DID is a read only register containing the device ID number of the CH7009 DID5 DID4 DID3 CH7009A Symbol: DID Address: 4Bh Bits DID2 DID1 DID0 201-0000-035 Rev 1.1, 5/8/2000 ...
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... Video level error VDD & AVDD current (simultaneous S-Video & 2 composite outputs) DVDD, TVDD (3.3V) current DVDD2 (1.8V) current (15pF load) 201-0000-035 Rev 1.1, 5/8/2000 Min - 0.5 1 GND - 0 Min 3.1 3.1 3.1 1 CH7009A Typ Max Units 5.0 V VDD + 0.5 V Indefinite Sec 85 C 150 C 150 C 220 C 5V can 0. Typ ...
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... DATA refers pin output refers to pixel data output Time - Graphics. P-OUT 44 Test Condition Min IOL = 2.0 mA 2.7 GND-0.5 Vref-0.25 GND-0.5 IOL = - 400 A DVDDV-0.2 IOL = 3.2 mA CH7009A Typ Max Unit 0.4 V DVDD + 0.5 V 1.4 V DVDD+0.5 V Vref+0. 0.2 V 201-0000-035 Rev 1.1, 5/8/2000 ...
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... CHRONTEL Mechanical Package Information 201-0000-035 Rev 1.1, 5/8/2000 CH7009A 45 ...
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... We provide no warranty for the use of our products and assume no liability for errors contained in this document. Printed in the U.S.A. 201-0000-035 Rev 1.1, 5/8/2000 ORDERING INFORMATION Package type Number of pins LQFP 64 Chrontel 2210 O’Toole Avenue San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com CH7009A Voltage supply 3.3V 46 ...