ch7004c Chrontel, ch7004c Datasheet

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... Patent number 5,781,241 ¥ Patent number 5,914,753 LINE YUV-RGB CONVERTER MEMORY TRUE SCALE SCALING & DEFLICKERING ENGINE SYSTEM CLOCK PLL TIMING & SYNC GENERATOR XCLK H Figure 1: Functional Block Diagram CH7004C TM D ESCRIPTION NTSC/PAL TRIPLE ENCODER DAC & FILTERS XI XO/FIN V CSYNC P-OUT BCO Y/R ...

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... CHRONTEL ESCRIPTIONS 3.1 Package Diagram 1 D[3] 2 D[4] 3 D[5] 4 D[6] 5 DVDD 6 D[7] 7 D[8] 8 DGND 9 D[9] 10 D[10] 11 D[11] 2 CHRONTEL CH7004 Figure 2: 44-pin LQFP 201-0000-024 Rev. 2.4, 6/24/2004 CH7004C 33 XO/FIN AVDD 30 DVDD 29 ADDR 28 DGND VDD 24 RSET 23 GND ...

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... In SCART mode, this pin outputs the red signal. Chrominance Output A 75 Ω termination resistor with short traces should be attached between C and ground for optimum performance. In normal operating modes other than SCART, this pin outputs the chroma video signal. In SCART mode, this pin outputs the green signal. CH7004C 3 ...

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... Application Information section. Digital Supply Voltage These pins supply the 3.3V power to the digital section of CH7004. Digital Ground These pins provide the ground reference for the digital section of CH7004, and MUST be connected to the system ground to prevent latchup. CH7004C 201-0000-024 Rev. 2.4, 6/24/2004 ...

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... RGB 24-bit YCrCb (24-bit) Cb,Y0,Cr,Y1,(CCIR656 style) RGB 24 8-8-8 over two words - ‘C’ version RGB 24 8-8-8 over two words - ‘I’ version RGB 24 (32) CH7004C Format Reference 5-6-5 each word 5-5-5 each word 5-5-5 over two bytes 5-6-5 over two bytes 8-8-8 over three bytes 8-8,8X over two words ...

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... Y0[7] R1[3] R2[4] R3[4] Y0[6] R1[2] R2[3] R3[3] Y0[5] R1[1] R2[2] R3[2] Y0[4] R1[0] R2[1] R3[1] Y0[3] G1[5] R2[0] R3[0] Y0[2] G1[4] G2[4] G3[4] Y0[1] G1[3] G2[3] G3[3] Y0[0] G1[2] G2[2] G3[2] Cb0[7] G1[1] G2[1] G3[1] Cb0[6] G1[0] G2[0] G3[0] Cb0[5] B1[4] B2[4] B3[4] Cb0[4] B1[3] B2[3] B3[3] Cb0[3] B1[2] B2[2] B3[2] Cb0[2] B1[1] B2[1] B3[1] Cb0[1] B1[0] B2[0] B3[0] Cb0[0] CH7004C HP1 HP P1a P1b P2a P2b YCrCb (16-bit Y1[7] Y2[7] Y3[7] Y1[6] Y2[6] Y3[6] Y1[5] Y2[5] Y3[5] Y1[4] Y2[4] Y3[4] Y1[3] Y2[3] Y3[3] Y1[2] Y2[2] Y3[2] Y1[1] Y2[1] Y3[1] Y1[0] Y2[0] Y3[0] Cr0[7] Cb2[7] Cr2[7] Cr0[6] Cb2[6] Cr2[6] Cr0[5] Cb2[5] Cr2[5] Cr0[4] Cb2[4] Cr2[4] Cr0[3] Cb2[3] Cr2[3] Cr0[2] Cb2[2] Cr2[2] ...

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... Y2[2] S[1] Y0[1] Y1[1] Y2[1] S[0] Y0[0] Y1[0] Y2[0] 00 Cb0[7] Cr0[7] Cb2[7] 0 Cb0[6] Cr0[6] Cb2[6] 0 Cb0[5] Cr0[5] Cb2[5] 0 Cb0[4] Cr0[4] Cb2[4] 0 Cb0[3] Cr0[3] Cb2[3] 0 Cb0[2] Cr0[2] Cb2[2] 0 Cb0[1] Cr0[1] Cb2[1] 0 Cb0[0] Cr0[0] Cb2[0] CH7004C Y3[7] Y4[7] Y5[7] Y3[6] Y4[6] Y5[6] Y3[5] Y4[5] Y5[5] Y3[4] Y4[4] Y5[4] Y3[3] Y4[3] Y5[3] Y3[2] Y4[2] Y5[2] Y3[1] Y4[1] Y5[1] Y3[0] Y4[0] Y5[0] Cr2[7] Cb4[7] Cr4[7] Cr2[6] Cb4[6] Cr4[6] Cr2[5] Cb4[5] Cr4[5] Cr2[4] Cb4[4] Cr4[4] Cr2[3] Cb4[3] ...

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... P2 t SP2 P0a P0b 7 RGB 5-6-5 P0b P1a P1b P0a R0[4] G1[2] R1[4] G0[2] R0[3] G1[1] R1[3] G0[1] R0[2] G1[0] R1[2] G0[0] R0[1] B1[4] R1[1] B0[4] R0[0] B1[3] R1[0] B0[3] G0[5] B1[2] G1[5] B0[2] G0[4] B1[1] G1[4] B0[1] G0[3] B1[0] G1[3] B0[0] 4 12-bit RGB (12-12) P0b P1a P1b P0a R0[7] G1[3] R1[7] G0[4] R0[6] G1[2] R1[6] G0[3] R0[5] G1[1] R1[5] G0[2] R0[4] G1[0] R1[4] B0[7] R0[3] B1[7] R1[3] B0[6] R0[2] B1[6] R1[2] B0[5] R0[1] B1[5] R1[1] B0[4] R0[0] B1[4] R1[0] B0[3] G0[7] B1[3] G1[7] G0[0] G0[6] B1[2] G1[6] B0[2] G0[5] B1[1] G1[5] B0[1] G0[4] B1[0] G1[4] B0[0] CH7004C t PH2 t HP2 t t SP2 HP2 t t SP2 HP2 P1a P1b P2a P2b 8 RGB 5-5-5 P0b P1a P1b x G1[2] x R0[4] G1[1] R1[4] R0[3] G1[0] R1[3] R0[2] B1[4] R1[2] R0[1] B1[3] R1[1] R0[0] B1[2] R1[0] G0[4] B1[1] G1[4] G0[3] B1[0] G1[3] 5 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[7] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 201-0000-024 Rev. 2.4, 6/24/2004 ...

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... Rev. 2.4, 6/24/2004 2 16-bit RGB (16-8) P0b P1a P1b A0[7] G1[7] R1[7] A0[6] G1[6] R1[6] A0[5] G1[5] R1[5] A0[4] G1[4] R1[4] A0[3] G1[3] R1[3] A0[2] G1[2] R1[2] A0[1] G1[1] R1[1] A0[0] G1[0] R1[0] R0[7] B1[7] A1[7] R0[6] B1[6] A1[6] R0[5] B1[5] A1[5] R0[4] B1[4] A1[4] R0[3] B1[3] A1[3] R0[2] B1[2] A1[2] R0[1] B0[1] A1[1] R0[0] B0[0] A1[0] 9 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7004C P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] 9 ...

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... S[ SP3 P0a P0b 6 RGB 8-bit P0b P0c P1a P1b G0[7] R0[7] B1[7] G1[7] G0[6] R0[6] B1[6] G1[6] G0[5] R0[5] B1[5] G1[5] G0[4] R0[4] B1[4] G1[4] G0[3] R0[3] B1[3] G1[3] G0[2] R0[2] B1[2] G1[2] G0[1] R0[1] B1[1] G1[1] G0[0] R0[0] B1[0] G1[0] CH7004C P2a P2b P3a P3b Cb2[7] Y2[7] Cr2[7] Y3[7] Cb2[6] Y2[6] Cr2[6] Y3[6] Cb2[5] Y2[5] Cr2[5] Y3[5] Cb2[4] Y2[4] Cr2[4] Y3[4] Cb2[3] Y2[3] Cr2[3] Y3[3] Cb2[2] Y2[2] Cr2[2] Y3[2] Cb2[1] Y2[1] Cr2[1] Y3[1] Cb2[0] Y2[0] Cr2[0] Y3[0] t PH3 t HP3 P0c P1a P1b P1c P1c P2a P2b ...

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... When genlocked, the CH7004 can also stop “dot crawl” motion (for composite mode operation in NTSC modes) to eliminate the annoyance of moving borders. Both of these features are under programmable control through the register set. 201-0000-024 Rev. 2.4, 6/24/2004 CH7004C 11 ...

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... CH7004C Pixel Horizontal Vertical Clock Total Total 24.671 784 525 28.196 784 600 30.210 800 630 39.273 1040 630 43.636 1040 700 47.832 1064 750 21.147 840 420 26.434 840 525 30 ...

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... Power is shut off to the unused DACs associated with S-Video outputs. In Composite-off state, power is shut off to the unused DAC associated with CVBS output. In this power-down state, all but the serial port circuits are disabled. This places the CH7004 in its lowest power consumption mode. CH7004C 13 ...

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... The composite luminance and chrominance frequency response is depicted in Figure 7 through Inc. and the customer. Luminance Bandwidth with Sin(X) /X (MHz) CVBS S-Video YCV YSV[1:0], YPEAK = 0.95 2.26 3.37 2.26 1.18 2.82 4.21 2.82 0.81 1.93 2.87 1.93 0.99 2.36 3.52 2.36 1.27 3.03 4.51 3.03 1.57 3.75 5.59 3.75 1.07 2.56 3.81 2.56 1.33 3.17 4.72 3.17 1.13 2.69 4.01 2.69 1.42 3.39 5.05 3.39 0.95 2.28 3.39 2.28 1.19 2.84 4.24 2.84 1.36 3.25 4.84 3.25 0.95 2.26 3.37 2.26 1.18 2.82 4.21 2.82 1.42 3.39 5.05 3.39 0.98 2.35 3.50 2.35 1.13 2.70 4.02 2.70 1.21 2.89 4.31 2.89 1.18 2.82 4.20 2.82 1.44 3.44 5.13 3.44 1.56 3.73 5.56 3.73 1.18 2.82 4.20 2.82 1.31 3.13 4.66 3.13 1.44 3.43 5.11 3.43 1.08 2.58 3.85 2.58 1.08 2.58 3.85 2.58 0.71 1.70 2.53 1.70 0.57 1.37 2.04 1.37 CH7004C S-Video YSV[1:0], YPEAK = 3.37 5.23 2.57 4.44 4.21 6.53 3.21 5.56 2.87 4.46 2.19 3.79 3.52 5.46 2.68 4.64 4.51 7.00 3.44 5.95 5.59 8.68 4.27 7.38 3.81 5.92 2.91 5.04 4.72 7.33 3.60 6.23 4.01 6.22 3.06 5.29 5.05 7.84 3.85 6.67 3.39 5.26 2.59 4.48 4.24 6.58 3.23 5.59 4.84 7.52 3.70 6.39 3.37 5.23 2.57 4.44 4.21 6.53 3.21 5.56 5.05 7.84 3.85 6.67 3.50 5.43 2.67 4.62 4.02 6.24 3.07 5.30 4.31 6.68 3.29 5.68 4.20 6.53 3.21 5.55 5.13 7.97 3.92 6.77 5.56 8.63 4.24 7.34 4.20 6.52 3.20 5.54 4.66 7.24 3.56 6.16 5.11 7.94 3.90 6.75 3.85 5.97 2.94 5.08 3.85 5.97 2.94 5.08 2.53 3.92 1.93 3.34 2.04 3.17 1.56 2.69 201-0000-024 Rev. 2.4, 6/24/2004 1X 5.23 6.53 4.46 5.46 7.00 8.68 5.92 7.33 6.22 7.84 5.26 6.58 7.52 5.23 6.53 7.84 5.43 6.24 6.68 6.53 7.97 8.63 6.52 7.24 7.94 5.97 5.97 3.92 3.17 ...

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... YSVdB (YSVdB ) n -24 -30 -36 - Figure 8: S-Video Luminance Frequency Response (YSV = 1X, YPEAK = 0) 201-0000-024 Rev. 2.4, 6/24/2004 n CH7004C ...

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... CHRONTEL -12 12 -18 18 < > i UVfirdB n <i> (UVfirdB ) n -24 24 -30 30 - Figure 9: Chrominance Frequency Response n CH7004C 201-0000-024 Rev. 2.4, 6/24/2004 ...

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... Active video and black ( times vary greatly due to different scaling ratios used in different modes. 4. Black times (F and H) vary with position controls. 201-0000-024 Rev. 2.4, 6/24/2004 The general parameters used to Level (mV) NTSC PAL 1.49 - 1.51 287 300 4. 0.59 - 0.61 287 300 2.50 - 2.53 287 300 1.55 - 1.61 287 300 0.00 - 7.50 340 300 37.66 - 52.67 340 300 0.00 - 7.50 340 300 CH7004C Duration (uS) NTSC PAL 1.48 - 1.51 4.69 - 4.71 0.88 - 0.92 2.24 - 2.26 2.62 - 2.71 0.00 - 8.67 34.68 - 52.01 0.00 - 8.67 17 ...

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... CH7004C 271 272 273 274 275 268 268 269 269 270 270 271 271 ...

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... FIE LD 4 FIE LD 4 312 313 314 315 316 317 312 313 314 315 316 317 4 3 ° ° ° ° ° ° CH7004C 318 318 319 319 320 320 321 321 322 322 323 323 6 ...

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... Figure 13: NTSC Y (Luminance) Output Waveform (DACG = 0) Color/Level mA V White 26.75 1.003 Yellow 24.62 0.923 Cyan 21.11 0.792 Green 18.98 0.712 Magenta 15.62 0.586 Red 13.49 0.506 Blue 10.14 0.380 Blank/ Black 8.00 0.300 Sync 0.00 0.000 Figure 14: PAL Y (Luminance) Video Output Waveform (DACG = 1) 20 Color bars: Color bars: 201-0000-024 Rev. 2.4, 6/24/2004 CH7004C ...

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... Yellow/Blue 23.93 0.897 Peak Burst 19.21 0.720 Blank 15.24 0.572 Peak Burst 11.28 0.423 Yellow/Blue 6.56 0.246 Green/Magenta 3.81 0.143 Cyan/Red 2.97 0.111 Figure 16: PAL C (Chrominance) Video Output Waveform (DACG = 1) 201-0000-024 Rev. 2.4, 6/24/2004 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7004C 21 ...

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... Peak Chrome 33.31 1.249 White 26.75 1.003 Peak Burst 11.97 0.449 Blank/Black 8.00 0.300 Peak Burst 4.04 0.151 Sync 0.00 0.000 Figure 18: Composite PAL Video Output Waveform (DACG = 1) 22 Color bars: 3.579545 MHz Color Burst (9 cycles) Color bars: 4.433619 MHz Color Burst (10 cycles) CH7004C 201-0000-024 Rev. 2.4, 6/24/2004 ...

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... P Ω and C, the total capacitance pF) P for the HIGH level, this input current limits the maximum value Ω (where and I DD input P CH7004C +VDD DATAN2 OUT SCLK DATA IN2 IN2 SLAVE ) input μ input μ ...

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... CH7004 at the register location specified by the address AR[5:0]. Register Address Byte (RAB AutoInc AR[ ACK Data ACK 1 CH7004 CH7004 acknowledge acknowledge AR[4] AR[3] CH7004C Alternating mode Stop Data n ACK CH7004 Condition acknowledge ADDR* ADDR R AR[2] AR[1] AR[0] 201-0000-024 Rev. 2.4, 6/24/2004 ...

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... Register Address Byte (RAB), is the data to be written into the register specified by AR[5:0]. If AutoInc = 0, then another RAB is expected from the master device, followed by another data byte, and so on. 201-0000-024 Rev. 2.4, 6/24/2004 SC from 1 Master Start Condition Figure 21: Acknowledge on the Bus CH7004C not acknowledge acknowledge clock pulse for acknowledgement 25 ...

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... CH7004 acknowledge acknowledge RAB ACK Data ACK Figure 22: Alternating Write Cycles CH7004 acknowledge RAB n ACK Data n CH7004C CH7004 CH7004 acknowledge acknowledge RAB ACK Data ACK Condition CH7004 CH7004 acknowledge acknowledge ACK ...

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... ACK Restart Condition Figure 24: Alternating Read Cycle CH7004 CH7004 acknowledge acknowledge Serial Port R/W*= ACK Restart Device ID R/W* Condition CH7004C CH7004 acknowledge Master does not acknowledge Serial Port R/W*= R/W* ACK Data 1 ACK Restart Condition Master does not acknowledge ...

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... Controls for the PLL and memory sections 21H 5 Control of CIV value 22H - 24H 8 each Readable register containing the calculated subcarrier increment value 25H 8 Device version number 26H - 29H 30 Reserved for test (details not included herein) 3FH 6 Current register being addressed CH7004C Functional Summary 201-0000-024 Rev. 2.4, 6/24/2004 ...

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... CIV5 CIV4 CIV3 VID5 VID4 VID3 TS1 TS0 RSA MS2 MS1 MSO YLM5 YLM4 YLM3 CLM5 CLM4 CLM3 AR5 AR4 AR3 CH7004C ) Bit 2 Bit 1 Bit 0 SR2 SR1 SR0 FY0 FT1 FT0 YSV1 YSV0 YCV IDF2 IDF1 IDF0 XCM0 PCM1 PCM0 SAV2 ...

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... CH7004C Symbol: DMR Address:00H Bits SR2 SR1 SR0 R/W R/W R Output Pixel Clock Format Scaling (MHz) PAL 5/4 21 ...

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... Settings for Chroma Channel 00 Minimal Flicker Filtering 01 Slight Flicker Filtering 10 Maximum Flicker Filtering 11 Enable Chroma DotCrawl Reduction 201-0000-024 Rev. 2.4, 6/24/2004 01 10 NTSC PAL FC1 FC0 FY1 R/W R/W R CH7004C 11 NTSC-J Symbol: FFR Address: 01H Bits FY0 FT1 FT0 R/W R/W R ...

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... This register sets the variables required to define the incoming pixel data stream CBW1 CBW0 YPEAK R/W R/W R RGBBP IDF3 R/W R CH7004C Symbol: VBW Address: 03H Bits YSV1 YSV0 YCV R/W R/W R Symbol: IDF Address: 04H Bits IDF2 ...

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... Display modes 25 and 26 must use a 2X multiplexed input data format and a 2X XCLK. Display modes 27 Note: and 28 must use a 1X XCLK input data format. 201-0000-024 Rev. 2.4, 6/24/2004 Description Reserved MCP XCM1 R/W R/W R CH7004C μ A, Symbol: CM Address: 06H Bits XCM0 PCM1 PCM0 R/W R/W R ...

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... SAV5 SAV4 SAV3 R/W R/W R CH7004C Symbol: SAV Address: 07H Bits SAV2 SAV1 SAV0 R/W R/W R 201-0000-024 Rev. 2.4, 6/24/2004 ...

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... Rev. 2.4, 6/24/2004 BL5 BL4 BL3 R/W R/W R HP5 HP4 HP3 R/W R/W R CH7004C Symbol: PO Address: 08H Bits SAV8 HP8 VP8 R/W R/W R Symbol: BLR Address: 09H Bits BL2 BL1 BL0 R/W R/W R/W 1 ...

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... Note: When sync direction is set output, horizontal sync will use a fixed pulse width of 64 pixels and vertical sync will use a fixed pulse width of 2 lines VP5 VP4 VP3 R/W R/W R DES R/W 0 CH7004C Symbol: VPR Address: 0BH Bits VP2 VP1 VP0 R/W R/W R Symbol: SPR Address: 0DH Bits ...

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... S-Video DACs are powered down All circuits and pins are active. All circuitry is powered down, except serial port circuit 1.235V). If the measured voltage is below this threshold value considered CH7004C Symbol: PMR Address: 0EH Bits PD2 PD1 PD0 ...

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... Normal Contrast = (17/16)*(Y -0) out in = (9/8)*(Y -0) out in = (5/4)*(Y -0) out in = (3/2)*(Y -0) = Enhances White out 128 160 192 CH7004C Symbol: CE Address: 11H Bits CE2 CE1 CE0 R/W R/W R 224 256 201-0000-024 Rev. 2.4, 6/24/2004 ...

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... Rev. 2.4, 6/24/2004 Reserved Reserved R/W R R/W R/W R R/W R/W R CH7004C Symbol: MNE Address: 13H Bits R/W R/W R Symbol: PLLM Address: 14H Bits R/W R/W R Symbol: PLLN Address: 15H Bits: 8 ...

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... PAL, 1 720X480, NTSC, 1 800X500, PAL, 1:1 190 13 28 640X400, NTSC, 1 SHF2 SHF1 SHF0 R/W R/W R CH7004C N 10 bits bits 9 3 110 63 126 63 190 89 647 313 86 33 284 103 302 242 197 ...

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... When the CH7004 is operating in the master clock mode, the tables below should be used to set the FSCI registers. When using these values, the ACIV bit in register 21H should be set to “0”, and the CFRB bit in register 06H should be set to “1”. 201-0000-024 Rev. 2.4, 6/24/2004 FSCI# R/W CH7004C Symbol: FSCI Address: 18H - 1FH Bits each FSCI# FSCI# ...

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... PAL-Nc (Argentina) “Normal Dot Crawl” 651,209,077 520,967,262 486,236,111 392,125,896 547,015,625 434,139,385 651,209,077 520,967,262 434,139,385 521,519,134 427,355,957 394,482,422 569,807,942 867,513,766 201-0000-024 Rev. 2.4, 6/24/2004 CH7004C PAL-M 762,524,467 622,468,953 573,798,541 463,452,668 645,523,358 516,418,687 451,866,351 622,468,953 544,660,334 508,349,645 521,384,251 469,245,826 428,083,911 568,782,819 ...

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... GPIOIN1 GPIOIN0 FSCI19 R/W R/W R GOENB1 GOENB0 FSCI15 R/W R/W R PLLCPI PLLCAP PLLS R/W R/W R CH7004C Address: 1BH Bits FSCI18 FSCI17 FSCI16 R/W R/W R Address: 1CH Bits FSCI14 FSCI13 FSCI12 R/W R/W R Symbol: PLLC Address: 20H Bits ...

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... See descriptions in the next section. 44 PLLCAP Value CIV25 CIV24 CH7004C Symbol: CIVC Address: 21H Bits CIVH1 CIVH0 ACIV R/W R/W R 201-0000-024 Rev. 2.4, 6/24/2004 ...

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... VID5 VID4 VID3 AR5 AR4 AR3 R/W R/W R CH7004C Symbol: CIV Address: 22H - 24H Bits CIV# CIV# CIV Symbol: VID Address: 25H Bits VID2 VID1 VID0 ...

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... RSET = 360 Ω, VREF = 1.235V, and NTSC CCIR601 operation. 46 Min - 0.5 1 GND - 0 The temperature requirements of vapor Min 4.75 4.75 3 Min Typ 9 9 33.89 105 40 CH7004C Typ Max Units 7.0 V VDD + 0.5 V Indefinite Sec °C 125 °C 150 °C 150 °C 260 °C 245 °C 225 ...

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... CHRONTEL Table 34. CH7004C Supply Current Characteristics Description Normal Operation IDD1 IDD2 IDD3 Normal Operation S-Video only IDD1 IDD2 IDD3 Normal Operation, composite only IDD1 IDD2 IDD3 Partial Power Down IDD1 IDD2 IDD3 Full Power Down IDD1 IDD2 IDD3 Notes The above data is typical with the following supply voltages: DVDD=3 ...

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... Pixel Clock High Time PH3 tdc3 Pixel Clock Duty Cycle (t 48 Test Condition IOL = 3.2 mA IOL = - 400 μA IOL = 3.2 mA Min PH1 PH2 PH3 P3 CH7004C Min Typ Max Unit 0 GND-0.5 1.4 V 2.5 DVDD+0.5 V GND-0.5 0.8 V 2.8 V 0.2 V Typ Max Unit 50 ...

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... Low Voltage Notes refers to all digital pixel and clock inputs. DATA refers to pixel data output. P-OUT 201-0000-024 Rev. 2.4, 6/24/2004 Test Condition Min IOL = 2.0 mA 2.7 GND-0.5 Vref+0.25 GND-0.5 IOL = - 400 μA 2.8 IOL = 3.2 mA CH7004C Typ Max Unit 0.4 V VDD + 0.5 V 1.4 V DVDD+0.5 V Vref-0. 0 ...

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... Hold time: t4 Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load PIXELS 1 VGA Line t5 DVDD2 - 0.2 CH7004C t4 t3 P0a P0b P1a P1b P2a P2b t5 t3 Min Typ Max Unit 1 ...

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... Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load 201-0000-024 Rev. 2.4, 6/24/2004 PIXELS 1 VGA Line t5 DVDD2 - 0.2 CH7004C P0a P0b P1a P1b P2a P2b t5 t3 Min Typ ...

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... Differential Clock: (XCLK = XCLK*) to (D[11:0 & VREF) Single-ended Clock: (XCLK =VREF) to (D[11:0 & VREF) t5 D[11:0 & DS rise/fall time w/15pF load Hold time: t6 P-OUT to HSYNC, VSYNC delay t7 (P-OUT=VREF) to (XCLK =XCLK*) delay PIXELS 1 VGA Line CH7004C P0a P0b P1a P1b P2a t3 Min Typ Max 1.7 3.6 DVDD2 - 0 ...

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... Dimension B: Top Package body size may be smaller than bottom package size by as much as 0.15 mm. Dimension B does not include allowable mold protrusions up to 0.25 mm per side. 201-0000-024 Rev. 2.4, 6/24/2004 SYMBOL 0.30 1.35 0.05 0.80 0.40 1.45 0.15 0.012 0.0531 0.00197 0.031 0.016 0.0571 0.0059 CH7004C LEAD E .004 0.50 0° 1.016 0.75 0.17 7° 0.0197 0° 0.040 0.0295 0.0067 7° 53 ...

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... Rev. 2.4, 6/24/2004 Disclaimer ORDERING INFORMATION Package type Number of pins LQFP 44 LQFP, Tape&Reel 44 LQFP, Lead Free 44 LQFP, Lead Free, 44 Tape&Reel Chrontel 2210 O’Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com CH7004C Voltage supply 3.3V/5V 3.3V/5V 3.3V/5V 3.3V/5V 54 ...