ch7004c Chrontel, ch7004c Datasheet - Page 41
ch7004c
Manufacturer Part Number
ch7004c
Description
Digital Pc To Tv Encoder With Macrovisiontm
Manufacturer
Chrontel
Datasheet
1.CH7004C.pdf
(54 pages)
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CHRONTEL
Sub-carrier Value Registers
The lower four bits of registers 18H through 1FH contain a 32-bit value which is used as an increment value for the
ROM address generation circuitry. The bit locations are specified as the following:
Register
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
When the CH7004 is operating in the master clock mode, the tables below should be used to set the FSCI registers.
When using these values, the ACIV bit in register 21H should be set to “0”, and the CFRB bit in register 06H should
be set to “1”.
201-0000-024 Rev. 2.4, 6/24/2004
Table 27. K3 Selection
Bit:
Symbol:
Type:
Default:
SHF[2:0]
000
010
011
100
101
110
111
7
Contents
FSCI[31:28]
FSCI[27:24]
FSCI[23:20]
FSCI[19:16]
FSCI[15:12]
FSCI[11:8]
FSCI[7:4]
FSCI[3:0]
K3
2.5
3.5
4.5
4
5
6
7
6
5
4
3
FSCI#
R/W
2
FSCI#
R/W
Symbol: FSCI
Address: 18H - 1FH
Bits: 4 or 8 each
1
FSCI#
R/W
CH7004C
0
FSCI#
R/W
41