edd51323dbh-ls Elpida Memory, Inc., edd51323dbh-ls Datasheet - Page 40
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edd51323dbh-ls
Manufacturer Part Number
edd51323dbh-ls
Description
512m Bits Ddr Mobile Ram
Manufacturer
Elpida Memory, Inc.
Datasheet
1.EDD51323DBH-LS.pdf
(59 pages)
- Current page: 40 of 59
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A READ Command to the Consecutive Precharge Command Interval
Operation by each case of destination bank of the consecutive Precharge command.
1.
2.
READ to PRECHARGE Command Interval (same bank) : To output all data
To complete a burst read operation and get a burst length of data, the consecutive precharge command must be
issued tRPD (= BL/ 2 cycles) after the read command is issued.
READ to PRECHARGE Command Interval (same bank): To stop output data
A burst data output can be interrupted with a precharge command. All DQ pins and DQS pins become high-Z tHZP
(= CL) after the precharge command.
Preliminary Data Sheet E1432E11 (Ver. 1.1)
Command
Command
Bank address
Same
Different
DQS
/CK
DQ
DQS
CK
READ to PRECHARGE Command Interval (same bank): To stop output data (CL = 3, BL = 4, 8)
/CK
DQ
CK
READ to PRECHARGE Command Interval (same bank): To output all data (CL = 3, BL = 4)
NOP
t0
t0
NOP
READ
t1
t1
Operation
The PRE and PALL command can interrupt a read operation.
To complete a burst read operation, tRPD is required between the read and the precharge
command. Please refer to the following timing chart.
The PRE command does not interrupt a read command.
No interval timing is required between the read and the precharge command.
tRPD = BL/2
NOP
READ
t2
t2
PRE/PALL
PRE/
PALL
t3
t3
out0 out1 out2 out3
40
t4
t4
tHZP
out0
t5
t5
out1
t6
NOP
t6
NOP
EDD51323DBH-LS
t7
t7
High-Z
High-Z
t8
t8
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