ch7301a ETC-unknow, ch7301a Datasheet

no-image

ch7301a

Manufacturer Part Number
ch7301a
Description
Chrontel Ch7301 Dvi Output Device
Manufacturer
ETC-unknow
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ch7301a-TF
Manufacturer:
CHRONTEL
Quantity:
20 000
CHRONTEL
Features
• DVI Transmitter up to 165MHz
• DVI low jitter PLL
• DVI hot plug detection
• Provides 10-bit high speed video DAC for RGB output
• DAC connection detect
• Programmable power management
• Fully programmable through I
• Complete Windows and DOS driver support
• Low voltage interface support to graphics device
• Offered in a 64-pin LQFP package
201-0000-036 Rev 1.1, 3/20/2000
XCLK,XCLK*
D[11:0]
H,V,DE
VREF
12
3
Chrontel CH7301 DVI Output Device
H,V,DE
Demux
Driver
Latch,
Clock
Latch
Data
HPDET
2
C port
GPIO[1:0]
*TMDS is Trademark of Silicon Image Inc
Figure 1: Functional Block Diagram
TLDET*
AS
Control
IIC
SC
General Description
The CH7301 is a Display controller device which accepts
a digital graphics input signal, and encodes and transmits
data through a DVI (TMDS
panel) can also be supported. The device accepts data
over one 12-bit wide variable voltage data port which
supports four different RGB data formats.
The DVI processor includes a low jitter PLL for
generation of the high frequency serialize clock, and all
circuitry required to encode, serialize and transmit data.
The CH7301 comes in versions able to drive a DFP
display at a pixel rate of up to 165MHz, supporting
UXGA resolution displays. No scaling of input data is
performed on the data output to the DVI device.
SD
Encode
DVI
BCO
DVI (TMDS
RESET*
Serialize
DVI
TM
link) PLL
Driver
Three
DAC's
8-bit
DVI
TM
link) or DFP (Digital flat
CH7301A
TLC,TLC*
TDC0,TDC0*
TDC1,TDC1*
TDC2,TDC2*
VSWING
R
G
B
ISET
C/H SYNC
1

Related parts for ch7301a

ch7301a Summary of contents

Page 1

... DVI device. DVI (TMDS DVI Encode IIC Control TLDET BCO Figure 1: Functional Block Diagram *TMDS is Trademark of Silicon Image Inc CH7301A TM link) or DFP (Digital flat TM link) PLL TLC,TLC* TDC0,TDC0* DVI DVI TDC1,TDC1* Serialize Driver TDC2,TDC2* VSWING ...

Page 2

... VREF DGND 6 GPIO[1] / TLDET GPIO[0] HPDET DGND DVDD 12 RESET AGND 16 2 Chrontel CH7301 Figure 2: 64-Pin LQFP CH7301A SYNC 47 BCO 46 TLDET* 45 DVDDV 44 AVDD GND 41 AGND 40 GND ISET 34 GND 33 VDD ...

Page 3

... This pin functions as the clock pin of the IIC interface port, and uses the DVDD supply. VSWING DVI Link Swing Control This pin sets the swing level of the DVI outputs. A 2.4K ohm resistor should be connected between this pin and TGND using short and wide traces. CH7301A TM link is 3 ...

Page 4

... I/O Supply Voltage TVDD DVI Transmitter Supply Voltage TGND DVI Transmitter Ground AVDD PLL Supply Voltage AGND PLL Ground VDD DAC Supply Voltage GND DAC Ground CH7301A TM differential outputs for data TM differential outputs for data TM differential outputs for data (3.3V) (3.3V - 1.1V) (3.3V) (3.3V) (3.3V) 201-0000-036 Rev 1.1, 3/20/2000 ...

Page 5

... These DVD compatible modes are input in a non-interlaced RGB data format 2 30Hz in progressive scan modes, 60Hz in interlaced modes 201-0000-036 Rev 1.1, 3/20/2000 Refresh Rate XCLK DVI (Hz) Frequency Frequency (MHz) (MHz) <85 <35.5 <355 <85 <31.5 <315 <85 <36 <360 59.94 27 270 50 27 270 <85 <57 <570 <85 <95 <950 <60 <67 <670 <85 <158 <1580 <60 <165 <1650 2 <140 <1400 <30 CH7301A 5 ...

Page 6

... VREF HPDET GPIO[1:0] TLDET* AS IIC SC Control SD BCO RESET DVI (TMDS PLL DVI DVI Encode Serialize Figure 3: DVI Output CH7301A TLC,TLC* TDC0,TDC0* DVI TDC1,TDC1* Dri v er TDC2,TDC2* VSWING CVBS (DAC3) Three Y (DAC 1) 8-bit C (DAC 2) DAC's CVBS (DAC0) ISET C/H SYNC ...

Page 7

... XCLK = XCLK* to D[11:0 & DE Delay (hold time) t2 DVDDV Digital I/O Supply Voltage 1 D[11:0 times measured when input equals Vref+100mV on rising edges, Vref-100mV on falling edges. 201-0000-036 Rev 1.1, 3/20/2000 P-OUT 1 VGA Line Figure 4: Interface Timing CH7301A t1 t2 Min Max Unit DVDDV - 0.2 DVDDV + 0.2 V -0.2 0.2 ...

Page 8

... Y1 byte refers to the next luminance sample, per CCIR-656 standards (the clock frequency is dependent upon the current mode, and is not 27MHz as specified in CCIR-656). All non-active pixels should RGB formats, and 16 for Y and 128 for CrCb in YCrCb formats. 8 CH7301A 201-0000-036 Rev 1.1, 3/20/2000 ...

Page 9

... P[7:0] (Blue Data) Figure 5: Multiplexed Input Data Formats (IDF = 0, 1) 201-0000-036 Rev 1.1, 3/20/2000 SAV P0a P0b P0b[11:4] P0b[3:0], P0a[11:8] P0b[11:7], P0b[3:1] P0b[6:4], P0a[11:9], P0b[0], P0a[3] P0a[8:4], P0a[2:0] CH7301A P1a P1b P2a P2b P1b[11:4] P2b[11:4] P2b[3:0], P1b[3:0], P1a[11:8] P2a[11:8] P0a[7:0] P1a[7:0] P2a[7:0] P2b[11:7] ...

Page 10

... The following data is latched for IDF = 4 CRA (internal signal) P[23:16] (Y Data) P[15:8] (CrCb Data) P[7:0] (ignored) Figure 6: 10 SAV P0a P0b Multiplexed Input Data Formats (IDF = CH7301A P1a P1b P2a P2b P0b[11:7] P1b[11:7] P2b[11:7] P2b[6:4], P0b[6:4], P0a[11:9] P1b[6:4], P1a[11:9] P2a[11:9] P0a[8:4] P1a[8:4] P2a[8:4] ...

Page 11

... RGB 5-6-5 P0b P1a P1b P0a R0[7] G1[4] R1[7] G0[5] R0[6] G1[3] R1[6] G0[4] R0[5] G1[2] R1[5] G0[3] R0[4] B1[7] R1[4] B0[7] R0[3] B1[6] R1[3] B0[6] G0[7] B1[5] G1[7] B0[5] G0[6] B1[4] G1[6] B0[4] G0[5] B1[3] G1[5] B0[3] 4 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7301A 1 12-bit RGB (12-12) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 3 RGB 5-5-5 P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] P2b P3a P3b Y2[7] ...

Page 12

... HPIR (Hot Plug Interrupt Reset) bit in register 1Eh high. The driver should then set the HPIR bit low YCrCb 8-bit P0b P1a P1b P2a 00 00 S[7] Cb2[ S[6] Cb2[ S[5] Cb2[ S[4] Cb2[ S[3] Cb2[ S[2] Cb2[ S[1] Cb2[ S[0] Cb2[0] CH7301A P2b P3a P3b Y2[7] Cr2[7] Y3[7] Y2[6] Cr2[6] Y3[6] Y2[5] Cr2[5] Y3[5] Y2[4] Cr2[4] Y3[4] Y2[3] Cr2[3] Y3[3] Y2[2] Cr2[2] Y3[2] Y2[1] Cr2[1] Y3[1] Y2[0] Cr2[0] Y3[0] 201-0000-036 Rev 1.1, 3/20/2000 ...

Page 13

... DVI PLL phase detector trim TPCP[1:0] DVI PLL charge pump trim TPVT[5:0] DVI PLL VDD trim TPVCO[10:0] DVI PLL VCO trim TPLPF[3:0] DVI PLL low pass filter DVID[3:0] DVI transmitter drive strength DVII DVI output invert CTL[3:0] DVI control inputs 201-0000-036 Rev 1.1, 3/20/2000 CH7301A 13 ...

Page 14

... and C, the total capacitance pF) P for the HIGH level, this input current limits the maximum value (where and I DD input P CH7301A +DVDD R P DATAN2 OUT SCLK DATA IN2 IN2 SLAVE ) input input 201-0000-036 Rev 1 ...

Page 15

... CH7301 at the register location specified by the address AR[6:0]. Register Address Byte (RAB AR[6] AR[5] 201-0000-036 Rev 1.1, 3/20/2000 ACK Data ACK 1 CH7301 CH7301 acknowledge acknowledge AR[4] AR[3] CH7301A Alternating mode Stop Data n ACK CH7301 Condition acknowledge R AR[2] AR[1] AR[0] 15 ...

Page 16

... Master Start Condition Figure 9: Acknowledge on the Bus CH7301 CH7301 acknowledge acknowledge RAB ACK Data ACK Figure 10: Alternating Write Cycles CH7301A not acknowledge acknowledge clock pulse for acknowledgment CH7301 CH7301 acknowledge acknowledge Stop RAB ACK ...

Page 17

... DAB, must be produced by the master before each of the RAB, and before each of the data read events. Two consecutive alternating read cycles are shown in Figure 12. 201-0000-036 Rev 1.1, 3/20/2000 CH7301 acknowledge RAB n ACK Data n CH7301A CH7301 CH7301 acknowledge acknowledge ACK Data n+1 ACK Condition ...

Page 18

... ACK Restart Device ID Condition Figure 12: Alternating Read Cycle CH7301 CH7301 acknowledge acknowledge ACK Restart Device ID R/W* Condition CH7301A CH7301 acknowledge Master does not acknowledge R/W* ACK Data 1 ACK Restart Condition Master does not acknowledge ...

Page 19

... TPVT5 TPVT4 TPVT3 TPLPF1 TPLPF0 TPVCO8 ResetIB ResetDB Reserved DACPD3 DACPD2 VID5 VID4 VID3 DID5 DID4 DID3 Reserved R/W CH7301A Bit 2 Bit 1 Bit 0 MCP Reserved XCM XCMD2 XCMD1 XCMD0 HPIE Reserved Reserved IDF2 IDF1 IDF0 DACT1 DACT0 SENSE DACG1 DACG0 DACBP ...

Page 20

... Bits 7-6 of register GPIO control the direction of the GPIO pins. A value of ‘1’ sets the corresponding GPIO pin to an input, and a value of ‘0’ sets the corresponding pin to an output R/W R/W R HPIR R/W R/W R CH7301A Symbol: IC Address: 1Dh Bits XCMD0 R/W R Symbol: GPIO Address: 1Eh Bits: 8 ...

Page 21

... A value of ‘0’ disables the interrupt signal. The GOENB1 control bit in register 1Eh should be set to ‘1’ when HPIE2 is set to ‘1’. 201-0000-036 Rev 1.1, 3/20/2000 R/W R/W R DVIT Reserved DACT2 CH7301A Symbol: IDF Address: 1Fh Bits IDF2 IDF1 IDF0 R/W R Symbol: CD Address: 20h ...

Page 22

... SYNCO1 SYNCO0 R/W R (Not Valid BCOP R/W R/W R BCO[2:0] Buffered Clock Output 100 (Not Valid) 101 (Not Valid) 110 VGA Vertical Sync 111 (Not Valid) CH7301A Symbol: DC Address: 21h Bits DACG1 DACG0 DACBP R/W R Symbol: BCO Address: 22h Bits ...

Page 23

... Rev 1.1, 3/20/2000 TPPD 1 TPPD 0 CTL3 R/W R/W R R/W R/W R DVID0 DVII Reserved Reserved R/W R/W R CH7301A Symbol: TCTL Address: 31h Bits CTL2 CTL1 CTL0 R/W R Symbol: TVCO Address: 32h Bits TPVCO0 R/W R Symbol: ...

Page 24

... Bit 2 of register TSTP is a test control, and should be left at the default value TPVT5 TPVT4 TPVT3 R/W R/W R TPLPF1 TPLPF0 Reserved Reserved Reserved R/W R/W R ResetIB ResetDB R/W R/W 1 CH7301A Symbol: TPVT Address: 35h Bits TPVT2 TPVT1 TPVT0 R/W R Symbol: TPF Address: 36h Bits Reserved R/W R ...

Page 25

... Is Operational When DVIP = 1 & FPD != 1 DVIL = 1 & FPD != 1 N/A DACPD2 != 1 & FPD != 1 DACPD1 != 1 & FPD != 1 DACPD0 != 1 & FPD != 1 FPD != VID5 VID4 VID3 CH7301A Symbol: PM Address: 49h Bits R/W R Symbol: VID Address: 4Ah Bits ...

Page 26

... R DEFAULT: TBD TBD Register DID is a read only register containing the device ID number of the CH7301 DID5 DID4 DID3 TBD TBD TBD CH7301A Symbol: DID Address: 4Bh Bits DID2 DID1 DID0 TBD TBD 201-0000-036 Rev 1.1, 3/20/2000 ...

Page 27

... Video D/A resolution Full scale output current Video level error VDD & AVDD current DVDD, TVDD (3.3V) current DVDD2 (1.8V) current (15pF load) 201-0000-036 Rev 1.1, 3/20/2000 Min - 0.5 1 GND - 0 Min 3.1 3.1 3.1 1 CH7301A Typ Max Units 5.0 V VDD + 0.5 V Indefinite Sec 85 C 150 C 150 C 220 C 5V can 0. Typ ...

Page 28

... DATA refers pin output refers to pixel data output Time - Graphics. P-OUT 28 Test Condition Min IOL = 2.0 mA 2.7 GND-0.5 Vref-0.25 GND-0.5 IOL = - 400 A DVDDV-0.2 IOL = 3.2 mA CH7301A Typ Max Unit 0.4 V DVDD + 0.5 V 1.4 V DVDD+0.5 V Vref+0. 0.2 V 201-0000-036 Rev 1.1, 3/20/2000 ...

Page 29

... CHRONTEL Mechanical Package Information 201-0000-036 Rev 1.1, 3/20/2000 CH7301A 29 ...

Page 30

... Printed in the U.S.A. 201-0000--036 Rev 1.1, 3/20/2000 ORDERING INFORMATION Number of pins Voltage supply Chrontel 2210 O’Toole Avenue San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com CH7301A Speed grade 3.3V 115MHz 3.3V 135MHZ 3.3V 165MHZ 30 ...

Related keywords