DS26303L-XXX DALLAS [Dallas Semiconductor], DS26303L-XXX Datasheet - Page 34
DS26303L-XXX
Manufacturer Part Number
DS26303L-XXX
Description
3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
Manufacturer
DALLAS [Dallas Semiconductor]
Datasheet
1.DS26303L-XXX.pdf
(101 pages)
- Current page: 34 of 101
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7 to 0: Automatic Transmit All-Ones Select Channel n (ATAOSn). When this bit is set an all-ones signal is
sent if a loss of signal is detected for LIUn. The all-ones signal uses MCLK as the reference clock.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 7: Receive Impedance Mode Select (RIMPMS). When this bit is set, the internal impedance mode is selected,
so all receive lines (RTIPn and RINGn) require no external resistance component. When this mode is selected, the
die-attach pad on the bottom of the package should be connected to ground for thermal dissipation. When reset,
external impedance mode is selected so all receive lines (RTIPn and RINGn) require external resistance. Note that
when in external impedance mode, if TS.RIMPOFF is reset, the resistance is still adjusted internally for the T1
(100Ω), J1 (110Ω), and E1(75Ω) modes of operation by the template selected so that only one resistor value is
required externally. In E1 (120Ω), external impedance mode has no need for any internal adjustment.
Bit 6: AIS Enable During Loss (AISEL). When this bit is set, for all channels, an AIS is sent to the system side
upon detecting an LOS on the corresponding channel. The individual settings in the
when this bit is set. When reset, the
Bit 5: Short-Circuit-Protection Disable (SCPD). If this bit is set, the short-circuit protection is disabled for all the
transmitters. The individual settings in
control.
Bit 4: Code (CODE). If this bit is set, AMI encoding/decoding is selected. The individual settings in register
are ignored when this bit is set. If reset, the
Bit 3: Jitter Attenuator Depth Select (JADS). If this bit is set the jitter attenuator FIFO depth is 128 bits. The
individual settings in register
Bit 1: Jitter Attenuator Position Select (JAPS). When the JAPS bit is set high, the jitter attenuator is in the
receive path, and when it is set low, it is in the transmit path. The individual settings in register
this bit is set. If reset, the
Bit 0: Jitter Attenuator Enable (JAE). When this bit is set the jitter attenuator is enabled. The individual settings in
register
IJAE
ATAOS8
RIMPMS
are ignored if this bit is set. If reset, the
7
0
7
0
ATAOS7
IJAPS
AISEL
6
0
6
0
IJAFDS
register has control.
ATAOS
Automatic Transmit All-Ones Select Register
0Eh
GC
Global Configuration Register
0Fh
IAISEL
are ignored if this bit is set. If reset, the
ATAOS6
ISCPD
SCPD
5
0
5
0
LCS
register has control.
are ignored when this bit is set. When reset, the
register has control.
ATAOS5
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
CODE
34 of 101
IJAE
4
0
4
0
register has control.
ATAOS4
JADS
3
0
3
0
IJAFDS
ATAOS3
—
2
0
2
0
register has control.
IAISEL
ATAOS2
JAPS
1
0
1
0
IJAPS
register are ignored
ISCPD
are ignored if
register has
ATAOS1
JAE
0
0
0
0
LCS
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