DS26303L-XXX DALLAS [Dallas Semiconductor], DS26303L-XXX Datasheet - Page 54
DS26303L-XXX
Manufacturer Part Number
DS26303L-XXX
Description
3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
Manufacturer
DALLAS [Dallas Semiconductor]
Datasheet
1.DS26303L-XXX.pdf
(101 pages)
- Current page: 54 of 101
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6 FUNCTIONAL DESCRIPTION
6.1 Power-Up and Reset
Internal power-on-reset circuitry generates a reset during power-up. All registers are reset to the default values.
Writing to the software-reset register generates at least a 1μs reset cycle, which has the same effect as the power-
up reset.
6.2 Master Clock
The receiver uses the MCLK as a reference for clock recovery, jitter attenuation, and generating RCLKn during
LOS. The DS26303 requires 2.048MHz ±50ppm or 1.544MHz ±50ppm or a multiple thereof. The AIS transmission
uses MCLK for transmit all-ones condition. See register
not set, MCLK is whatever the incoming frequency is.
MCLK or RCLK can be used to output CLKA. Register
TECLK. Any RCLKn can be selected as an input to the clock generator using this same register. For a detailed
description of selections available, see
Figure 6-1. Prescaler PLL and Clock Generator
MCLK
MPS1..0
Scaler
PLL
Pre
FREQS
RLCK1..8
PLLE
PLLE
Figure
T1CLK
E1CLK
6-1.
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
54 of 101
CCR
PCLKS2..0
MC
is used to select the clock generated for CLKA and the
to set desired incoming frequency. If the PLLE bit is
PCLKI1..0
TECLKS
CLKA3..0
GEN
CLK
TECLKI
RLOS1
RLOS16
CLKAI
TECLKE
CLKAE
TECLK
CLKA
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