DS26303L-XXX DALLAS [Dallas Semiconductor], DS26303L-XXX Datasheet - Page 68
DS26303L-XXX
Manufacturer Part Number
DS26303L-XXX
Description
3.3V, E1/T1/J1, Short-Haul, Octal Line Interface Unit
Manufacturer
DALLAS [Dallas Semiconductor]
Datasheet
1.DS26303L-XXX.pdf
(101 pages)
- Current page: 68 of 101
- Download datasheet (2Mb)
6.9 BERT
The BERT is a software-programmable test-pattern generator and monitor capable of meeting most error-
performance requirements for digital transmission equipment. It generates and synchronizes to pseudorandom
patterns with a generation polynomial of the form x
repetitive patterns of any length up to 32 bits.
The transmit direction generates the programmable test pattern, and inserts the test pattern payload into the data
stream.
The receive direction extracts the test pattern payload from the receive data stream, and monitors the test pattern
payload for the programmable test pattern. The features include:
•
•
•
•
•
6.9.1 Configuration and Monitoring
Set BTCR:BERTE = 1 to enable the BERT. The following tables show how to configure the on-board BERT to send
and receive common patterns.
Table 6-10. Pseudorandom Pattern Generation
2
2
(2047 type)
2
2
2
2
Table 6-11. Repetitive Pattern Generation
All 1s
All 0s
Alternating 1s and 0s
Double alternating and 0s
3 in 24
1 in 16
1 in 8
1 in 4
9
11
15
20
20
23
-1 O.153 (511 type)
-1 O.152 and O.153
-1 O.151
-1 O.153
-1 O.151 QRSS
-1 O.151
PATTERN TYPE
Programmable PRBS pattern. The pseudorandom bit sequence (PRBS) polynomial (x
are programmable (length n = 1 to 32, tap y = 1 to n – 1, and seed = 0 to 2
Programmable repetitive pattern. The repetitive pattern length and pattern are programmable (the length n =
1 to 32 and pattern = 0 to 2
24-bit error count and 32-bit bit count registers
Programmable bit-error insertion. Errors can be inserted individually, on a pin transition, or at a specific rate.
The rate 1/10
Pattern synchronization at a 10
random bit-error rate (BER) of 10
PATTERN TYPE
n
is programmable (n = 1 to 7).
PTF[4:0]
(hex)
0D
n
04
08
10
02
11
– 1).
PTF[4:0]
(hex)
NA
NA
NA
NA
NA
NA
NA
NA
-3
BPCR
.
-3
PLF[4:0]
BER. Pattern synchronization is achieved even in the presence of a
(hex)
BPCR
0A
0E
08
13
13
16
REGISTER
PLF[4:0]
(hex)
0F
00
00
01
03
17
07
03
REGISTER
n
DS26303: 3.3V, T1/E1/J1, Short-Haul, Octal Line Interface Unit
+ x
68 of 101
PTS
0
0
0
0
0
0
y
+ 1, where n and y can take on values from 1 to 32 and to
PTS
1
1
1
1
1
1
1
1
QRSS
0
0
0
0
1
0
QRSS
0
0
0
0
0
0
0
0
0x0D0E
0x080A
0x0408
0x1013
0x0253
0x1116
BERT.
PCR
0x0021
0x002F
0x0020
0x0020
0x0023
0x0037
0x0027
0x0023
BERT.
PCR
n
– 1).
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
BERT.
SPR2
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFF20
BERT.
SPR2
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xFFFF
BERT.
SPR1
n
+ x
0xFFFE
0xFFFE
0xFFFC
0xFFFF
0xFFF1
0xFF01
0x0022
0x0001
y
BERT.
SPR1
+ 1) and seed
BERT.CR
TPIC,
RPIC
0
0
1
0
0
1
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