eds1232aase Elpida Memory, Inc., eds1232aase Datasheet - Page 48

• Manufacturer Part Number: eds1232aase
• Description: 128m Bits Sdram
• Manufacturer: Elpida Memory, Inc.

Self Refresh Cycle
Clock Suspend Mode
Data Sheet E0350E31 (Ver. 3.1)
DQ (output)
DQ (output)
DQ (output)
DQ (input)
DQ (input)
DQ (input)
Address
Address
Address
/RAS
/CAS
DQM
/RAS
/CAS
DQM
/RAS
/CAS
DQM
CKE
CKE
CKE
CLK
CLK
/WE
/WE
/WE
/CS
/CS
/CS
BS
BS
BS
Precharge command
If needed
Bank0
Active
Bank0
Active
R:a
R:a
A10=1
0
Active clock
suspend start
Active clock
suspend start
1
t
RP
2
Self refresh entry
command
3
Active clock
supend end
Active clock
suspend end
4
CKE Low
tSI
5
Bank0
Write
C:a
Bank0
Read
C:a R:b
a
6
Bank3
Active
a+1 a+2
7
Bank3
Active
a
R:b
tHI
Write suspend
8
Self refresh exit
ignore command
or No operation
start
a+1 a+2
Read suspend
9
High-Z
lSREX
start
10
48
High-Z
Write suspend
11
t
High-Z
RC
Read suspend
tSI
a+3
end
12
Next
clock
enable
Bank3
Write
end
C:b
b
13
Bank3
Read
a+3
Bank0
Precharge
b+1 b+2 b+3
Self refresh entry
command
C:b
14
Bank0
Precharge
15
b
16
b+1 b+2
17
Earliest Bank3
Precharge
Earliest Bank3
Precharge
t
RC
18
Next
clock
enable
b+3
19
Auto
refresh
EDS1232AASE
20
Write cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
Read cycle
/RAS-/CAS delay = 2
/CAS latency = 2
Burst length = 4
Self refresh cycle
/RAS-/CAS delay = 3
CL = 3
BL = 4
= VIH or VIL
= VIH or VIL
= VIH or VIL