UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 101
Manufacturer Part Number
4 BIT SINGLE-CHIP MICROCOMPUTER
In the SBI mode, the master usually selects a slave device to communicate with from multiple
devices by outputting the address of the slave in the serial bus.
After selecting a device to communicate with, the master exchanges commands and data with
the slave device, thus establishing serial communication.
Fig. 4-54 to 4-57 show the timing charts of data communication operations.
In the SBI mode, the shift register 0 performs shift operation on the falling edge of the serial clock
(SCK0). Send data is held on the SO0 latch, and is output on the SB0/P02 or SB1/P03 pin starting
with the MSB. Receive data applied to the SB0 (or SB1) pin is latched in the shift register 0 on
the rising edge of SCK0.