UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 57

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

(7) Procedure for changing the system clock and CPU clock
The procedure for changing the system clock and CPU clock is explained using Fig. 4-19.
Remark The values not enclosed in square brackets are for f
Notes 1. 15.3 s at 4.19 MHz
Commercial
power
line voltage
1
2
3
4
V
A RESET input starts CPU operation at the lowest speed of the main system clock (10.7 s
at 6.0 MHz)
The PCC is rewritten for highest-speed operation after a time elapse which is sufficient for the voltage
on the V
The removal of commercial power is detected using, for example, an interrupt input (INT4 is useful),
then SCC.0 is set to operate with the subsystem clock. (In this case, the start of subsystem clock
generation must be confirmed beforehand.) After a time (32 machine cycles) required to switch to
the subsystem clock elapses, SCC.3 is set to terminate main system clock generation.
After detecting the input of commercial power by using an interrupt, SCC.3 is cleared to start main
system clock generation. After a time required for stable generation, SCC.0 is cleared to operate at
highest speed.
DD
System clock
RESET signal
pin voltage
2. 31.3 ms at 4.19 MHz
CPU clock
enclosed in square brackets for f
OFF
DD
ON
pin to be high enough for highest-speed operation.
Note 1
Fig. 4-19 Changing the System Clock and CPU Clock
after a wait time (21.8 ms at 6.0 MHz)
Internal reset
operation
Wait 21.8 ms [31.3 ms]
[15.3 s]
10.7 s
f
X
X
= 4.19 MHz.
[0.95 s]
0.67 s
X
f
X
= 6.0 MHz and f
Note 2
for stable oscillation.
XT
= 32.768 kHz; the values
122 s
f
XT
PD75238
[0.95 s]
0.67 s
f
X
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