UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 65
UPD75238GJ
Manufacturer Part Number
UPD75238GJ
Description
4 BIT SINGLE-CHIP MICROCOMPUTER
Manufacturer
NEC [NEC]
Datasheet
1.UPD75238GJ.pdf
(190 pages)
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(2) Timer/event counter mode register (TM0) and timer/event counter output enable flag (TOE0)
The timer/event counter mode register (TM0) is an 8-bit register for controlling the timer/event counter.
It is set by an 8-bit memory manipulation instruction.
Fig. 4-27 shows the format of the timer/event counter mode register.
Bit 3 is the timer start bit, and can be set independently of the other bits. Bit 3 is automatically reset to
0 when the timer starts operation.
A RESET input clears all the bits of the TM0 to 0.
The timer/event counter output enable flag (TOE0) enables or disables output of the timer out F/F (TOUT
F/F) status to the PTO0 pin.
Fig. 4-26 shows the format of the timer/event counter output enable flag.
The timer out F/F (TOUT F/F) can be inverted by a match signal sent out from the comparator. The timer
out F/F is reset when an instruction sets bit 3 of the TM0.
A RESET input clears the TOE0 and TOUT F/F to 0.
Fig. 4-26 Format of the Timer/Event Counter Output Enable Flag
Address
FA2H
TOE0
3
Timer/event counter output enable flag
0
1
Disables
Enables
PD75238
65
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