UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 83

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

Serial clock selection bit (W)
Serial interface operation mode selection bit (W)
Wake-up function specification bit (W)
CSIM01
CSIM04
WUP
Note The values in parentheses are for f
Remark
Caution When WUP = 1 is set during BUSY signal output, BUSY is not released. In the SBI mode, the
0
0
1
1
0
1
0
1
CSIM00
CSIM03
0
1
BUSY signal is output until the next falling edge of the serial clock (SCK0) appears after release
of BUSY is directed. Before setting WUP = 1, be sure to confirm that the SB0 (or SB1) pin is high
after releasing BUSY.
: Don’t care
0
1
0
1
0
1
1
Sets IRQCSI0 each time serial transfer is completed in each mode.
Used in the SBI mode only to set IRQCSI0 only when an address received after bus release matches
the data in the slave address register (wake-up state). SB0/SB1 goes to high-impedance state.
Fig. 4-40 Format of Serial Operation Mode Register 0 (CSIM0) (2/3)
CSIM02
3-wire serial I/O mode
0
1
0
1
f
f
X
X
/2
/2
3-wire serial I/O
mode
SBI mode
2-wire serial I/O
mode
4
3
Operation mode
(262 kHz or 375 kHz)
(524 kHz or 750 kHz)
External clock applied to SCK0 pin
Time/event counter output (T0)
X
= 4.19 MHz or 6.0 MHz.
Serial clock
SBI mode
Note
Note
SIO0
(Transfer starting
with MSB)
SIO0
(Transfer starting
with LSB)
SIO0
(Transfer starting
with MSB)
SIO0
(Transfer starting
with MSB)
Bit sequence for
shift register 0
7-0
0-7
7-0
7-0
XA
XA
XA
XA
2-wire serial I/O mode
f
X
/2
6
SO0/P02
(CMOS output)
SB0/P02
(N-ch open-drain
input/output)
P02 input
SB0/P02
(N-ch open-drain
input/output)
P02 input
(65.5 kHz or
93.8 kHz)
SO0 pin function
Note
SI0/P03
(Input)
P03 input
SB1/P03
(N-ch open-drain
input/output)
P03 input
SB1/P03
(N-ch open-drain
input/output)
SCK0 pin mode
SI0 pin function
Output
PD75238
Input
83