UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 87

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

Bus release trigger bit (W)
Command trigger bit (W)
Bus release detection flag (R)
Command detection flag (R)
Acknowledge trigger bit (W)
Acknowledge enable bit (R/W)
CMDT
CMDD
RELD
ACKE
RELT
ACKT
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial
Cautions 1. Never set ACKT before or during serial transfer.
Control bit for bus release signal (REL) trigger output.
By setting RELT = 1, the SO0 latch is set to 1. Then the RELT bit is automatically cleared to 0.
Control bit for command signal (CMD) trigger output.
By setting CMDT = 1, the SO0 latch is cleared to 0. Then the CMDT bit is automatically cleared to 0.
1
2
3
4
When set after transfer, ACK is output in phase with the next SCK0. After ACK signal output, this bit is auto-
matically cleared to 0.
1
2
3
4
0
1
transfer.
transfer.
2. ACKT cannot be cleared by software.
3. Before setting ACKT, set ACKE = 0.
The transfer start instruction is executed.
The RESET signal is entered.
CSIE0 = 0 (See Fig. 4-40.)
SVA does not match SIO0 when an address is
received.
The transfer start instruction is executed.
The bus release signal (REL) is detected.
The RESET signal is entered.
CSIE0 = 0 (See Fig. 4-40.)
Condition for being cleared (CMDD = 0)
Condition for being cleared (RELD = 0)
When set before transfer
When set after transfer
Disables automatic output of the acknowledge signal (ACK). (Output by ACKT is possible.)
Fig. 4-41 Format of Serial Bus Interface Control Register (SBIC) (2/3)
ACK is output in phase with the 9th clock of SCK0.
ACK is output in phase with SCK0 immediately following set
instruction execution.
The bus release signal (REL) is detected.
The command signal (CMD) is detected.
Condition for being set (CMDD = 1)
Condition for being set (RELD = 1)
PD75238
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