UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 91

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

Bus release signal
(REL)
Command signal
(CMD)
Acknowledge
signal
(ACK)
Busy signal
(BUSY)
Ready signal
(READY)
Signal name
Master
Master
Master/
slave
Slave
Slave
Output
device
Rising edge of SB0/SB1
when SCK0 = 1
Falling edge of SB0/SB1
when SCK0 = 1
Low level signal
output on SB0/SB1
during one SCK0 clock
cycle after serial
receive operation is
completed
[Synchronous busy
signal]
Low level signal output
on SB0/SB1 after
acknowledge signal
High level signal
output on SB0/SB1
before serial transfer
is started or after
serial transfer is
completed
Definition
Table 4-6 Various Signals Used in the SBI Mode (1/2)
[Synchronous busy signal output]
SCK0
SB0/
SB1
SB0/
SB1
SB0/SB1
SB0/SB1
SCK0
SCK0
D0
D0
9
ACK
Timing chart
“H”
“H”
ACK
BUSY
BUSY
READY
READY
• RELT is set.
• CMDT is set.
# ACKE = 1
$ ACKT is set.
• BSYE = 1
# BSYE = 0
$ Execution of
Condition for
output
instruction to
write data to
SIO0 (direction
to start transfer)
• RELD is set.
• CMDD is clear-
• CMDD is set.
• ACKD is set.
ed.
Flag
operation
–
–
Indicates that CMD
signal follows and
data sent is address
data.
ii) Data sent, with
Indicates completion
of receive operation.
Indicates that serial
receive operation is
disabled because
processing is in
progress.
Indicates that serial
receive operation is
enabled.
i) Data sent after
REL signal output
is address.
REL signal not
being output, is
command.
Meaning
of signal