UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 93

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UPD75238GJ

Manufacturer Part Number
UPD75238GJ
Description
4 BIT SINGLE-CHIP MICROCOMPUTER
Manufacturer
NEC [NEC]
Datasheet
SO0 latch
SO0 latch
RELT
(Master)
CMDT
(Master)
Caution Do not set the ACKT until the transfer is completed.
CMDD
CMDD
Set after transfer completion.
CMDT
RELD
RELD
SCK0
SCK0
RELT
SIO0
SIO0
SB0/SB1
ACKT
SCK0
Transfer operation start specification
6
"H"
Fig. 4-43 Operations of RELT, CMDT, RELD, and CMDD (Master)
D2
Fig. 4-44 Operations of RELT, CMDT, RELD, and CMDD (Slave)
7
D1
8
D0
Fig. 4-45 Operation of ACKT
9
D7
When set during this period
1
D6
2
D1
7
ACK
D0
8
ACK signal is output during first clock
cycle immediately after ACKT is set.
When address match is found
When address mismatch is found
Transfer operation start specification
Write to SIO0
PD75238
93

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