UPD75238GJ NEC [NEC], UPD75238GJ Datasheet - Page 98

• Manufacturer Part Number: UPD75238GJ
• Description: 4 BIT SINGLE-CHIP MICROCOMPUTER
• Manufacturer: NEC [NEC]

SB0/SB1
IRQCSI0
98
SCK0
(c) Two-wire serial I/O mode
The two-wire serial I/O mode can be made compatible with any communication format by programming.
In this mode, communication is basically performed using two lines: Serial clock (SCK0) and serial
data input/output (SB0 or SB1).
(i)
Communication operation
The two-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit
by bit in phase with the serial clock.
The shift register 0 performs shift operation on the falling edge of the serial clock (SCK0). Send
data is latched on the SO0 latch, and is output on the SB0/P02 pin or SB1/P03 pin starting with
the MSB. Receive data applied to the SB0 pin or SB1 pin is latched in the shift register 0 on the
rising edge of SCK0.
When eight bits have been transferred, shift register 0 operation automatically terminates setting
the interrupt request flag (IRQCSI0).
The SB0 or SB1 pin becomes an N-ch open-drain I/O when specified as the serial data bus, so
the voltage level on that pin must be pulled up externally.
The state of the SO0 latch is output on the SB0 or SB1 pin, so the SB0 or SB1 pin output states
can be controlled by setting the RELT or CMDT bit.
However, this operation must not be performed during serial transfer operation.
The output state of the SCK0 pin can be controlled by manipulating the P01 output latch in the
output mode (internal system clock mode). (See (7) in Section 4.9.)
Fig. 4-51 Timing of Two-Wire Serial I/O Mode
1
D7
2
Transfer operation is started in phase with falling edge of SCK0.
Execution of instruction that writes date to SIO0 (Transfer operation start spcification)
D6
3
D5
4
D4
5
D3
6
D2
7
D1
Completion of transfer
8
PD75238
D0