PLL103-02D PhaseLink (PLL), PLL103-02D Datasheet - Page 6
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PLL103-02D
Manufacturer Part Number
PLL103-02D
Description
Standard Clock Buffer (SDRAM And DDR) , 12x2 Ddr, 66 - 170MHz in
Manufacturer
PhaseLink (PLL)
Datasheet
1.PLL103-02D.pdf
(7 pages)
3. Electrical Specifications (Continued)
Note: TBM: To be measured
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Supply Current
Output Crossing
Voltage
Output Voltage
Swing
Duty Cycle
Max. Operating
Frequency
Rising Edge Rate
Falling Edge Rate
Clock Skew ( pin to
pin )
Stabilization Time
PARAMETERS
DDR SDRAM Buffer for Desktop PCs with 4 DDR DIMMS
SYMBOL
T
V
I
V
T
T
T
SKEW
DDS
D
OUT
OC
OR
OF
ST
T
PD = 0
Measured @ 1.5V
Measured @
Measured @
All outputs equally loaded
CONDITIONS
2.4V ~ 0.4V
0.4V ~ 2.4V
(VDD/2)
MIN.
PLL103-02 Rev.D
-0.1
1.1
1.0
1.0
45
66
VDD/2
TYP.
1.5
1.5
50
(VDD/2)+
VDD-0.4
MAX.
TBM
170
100
Rev 01/11/01 Page 6
0.1
2.0
2.0
0.1
55
UNITS
MHz
V/ns
V/ns
mA
ms
ps
%
V
V