PLL130-07 PhaseLink (PLL), PLL130-07 Datasheet - Page 2

• Manufacturer Part Number: PLL130-07
• Description: Output Level Converter Buffer , 1 Out, Translator to STD Drive CMOS, < 200MHz
• Manufacturer: PhaseLink (PLL)

PIN DESCRIPTION
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for INDUSTRIAL grade only.
2. AC Specification
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
Supply Voltage Range
Input Voltage Range
Output Voltage Range
Soldering Temperature
Storage Temperature
Ambient Operating Temperature*
Input Frequency
Input signal swing
Output Frequency
DRIV_SEL
CLK_OUT
REF_IN
Name
GND
VDD
OE
PARAMETERS
Pin number
8pin SOIC
1,3,6
N/A
4,7
8
2
5
High Speed Translator Buffer to CMOS (Selectable Drive)
PARAMETERS
3x3mm QFN
Pin number
7,10,11,12
1,2,4,5,
9,14,15
13
16
3
8
REF_IN input
Type
O
P
P
I
I
I
CONDITIONS
Ground connector
3.3V Power supply
Drive Select input: ‘1’ for standard drive, ‘0’ for hi-drive output.
Internal pull-up (default is ‘1’).
Reference input signal. The frequency of this signal will be
reproduced at the output (after translation to CMOS level).
CMOS clock output.
Output enable (‘1’ for enable). Internal pull-up (default is ‘1’).
SYMBOL
V
V
T
T
V
CC
O
S
A
I
Preliminary
MIN.
100
MIN.
0
0
-
-
-
Description
-65
-40
0.5
0.5
0.5
TYP.
PLL130-07
V
V
MAX.
CC
CC
260
150
85
7
+
+
0.5
0.5
Rev 10/29/02 Page 2
MAX.
200
200
UNITS
UNITS
V
V
V
MHz
MHz
C
C
C
mV