PLL202-108 PhaseLink (PLL), PLL202-108 Datasheet - Page 12

• Manufacturer Part Number: PLL202-108
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

15. Byte 14: SKEW Control Register
TABLE 2: Output Drive Strength Programming Summary:
16. Byte 15: Buffer Drive Strength Control Register
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Bit<2:0>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
111
110
101
100
011
010
001
000
Default
+40%
+30%
+20%
+10%
Strength
-10%
-20%
-30%
Skew
Skew
AGP
AGP
PCI
Name
Name
Setting I
-
-
Setting applies to the
following outputs
1. AGP[0:1]
2. 48M, 24_48MHz
-
-
-
-
-
Programmable Clock Generator for ALI 1681 P4 Chip Sets
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Bit <2>
Bit <1>
Bit <0>
Default
Default
0
0
0
1
1
0
1
1
0
0
0
0
0
0
1
1
Default
+50%
+38%
+25%
+13%
-13%
-25%
-38%
Reserved.
Reserved.
These three bits will adjust timing of AGP0 and AGP1 clock
signals either positive or negative delay up to +640ps or –480ps
with ±160ps per step and ± 5% accuracy.
These three bits will adjust timing of all PCI clock signals either
positive or negative delay up to +640ps or –480ps with ±160ps
per step and ± 5% accuracy.
Reserved.
Reserved.
Reserved.
Reserved.
Reserved.
These three bits will program drive strength for all AGP clocks
output clock (see Table 2).
Setting II
Setting applies to the
following outputs
1. PCIF,PCI[5:8]
2. PCI[0:4]
3. REF[0:1]
Description
Description
PLL202-108
Rev 8/20/02 Page 12