ssd1800 ETC-unknow, ssd1800 Datasheet
ssd1800
Related parts for ssd1800
ssd1800 Summary of contents
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... SEMICONDUCTOR TECHNICAL DATA LCD Segment / Common Driver with Controller for Character Display System This document contains information on a new product. Specifications and information herein are subject to change without notice. http://www.solomon-systech.com SSD1800 Series Rev 1.0 P 1/42 SSD1800 Advance Information 80x16 + 1 Icon line Copyright 2004 Solomon Systech Limited ...
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... TABLE OF CONTENTS 1 GENERAL DESCRIPTION ................................................................................................................. 5 2 FEATURES ......................................................................................................................................... 5 3 ORDERING INFORMATION............................................................................................................... 5 4 BLOCK DIAGRAM ............................................................................................................................. 6 5 PIN ARRANGEMENT OF SSD1800Z GOLD BUMP DIE .................................................................. 7 6 PIN ARRANGEMENT OF SSD1800AV BARE DIE ......................................................................... 10 7 PIN DESCRIPTIONS ........................................................................................................................ 12 8 FUNCTIONAL BLOCK DESCRIPTIONS ......................................................................................... 15 9 VOLTAGE GENERATOR CIRCUIT ................................................................................................. 24 10 FRAME FREQUENCY ...................................................................................................................... 25 11 COMMAND TABLE .......................................................................................................................... 26 12 COMMAND DESCRIPTIONS ...
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... TABLE OF TABLES Table 1 - Ordering Information .................................................................................................................. 5 Table 2 - SSD1800Z Gold Bump Die Pad Coordinates ............................................................................ 8 Table 3 - SSD1800AV Bare Die Pad Coordinates................................................................................... 11 Table 4 - Relationship between ICONRAM Address and Display Pattern........................................... 18 Table 5 - CGROM Character Code ........................................................................................................... 19 Table 6 - Relationship between Character Code (DDRAM) and Character Pattern (CGRAM)........... 20 Table 7- Contrast Control Register ......................................................................................................... 22 Table 8 - Command Table ...
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... TABLE OF FIGURES Figure 1 - Block Diagram of SSD1800....................................................................................................... 6 Figure 2 - SSD1800Z Pin Arrangement ..................................................................................................... 7 Figure 3 - SSD1800AV Pin Arrangement ................................................................................................ 10 Figure 4 - Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (6800 MPU Mode) ................... 16 Figure 5 - Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (8080 MPU Mode) ................... 16 Figure 6 - Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (6800 MPU Mode) ................... 17 Figure 7 - Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (8080 MPU Mode) ...
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... It can display 2 lines of 16 characters with 5x8 dots format. The double height character mode and line vertical scroll functions are supported. SSD1800 displays character directly from its internal 10,240 bits (256 characters dots) Character Generator ROM (CGROM). All the character codes are stored in the 512 bits (16 characters x 4 lines) Data Display RAM (DDRAM) ...
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... M i Character Generator RAM (CGROM) Display Data RAM (CGRAM) Icon RAM (DDRAM) (ICONRAM) Command Decoder R/W C68 RD) (WR) (SDA) Figure 1 – Block Diagram of SSD1800 Mar 2004 Level Selector Regulated DC/DC Converter, Voltage Divider, Contrast Control Parallel/ Serial Interface ...
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... PIN ARRANGEMENT OF SSD1800Z GOLD BUMP DIE Alignment Keys 26.3 µm 26.3 µm 26.3 µm X Center (-2940.9, 480.0) 8.75µm 37.6µm X (-2835, -598.5) Figure 2 - SSD1800Z Pin Arrangement Die Size: 6170um x 1480um (include scribe line) 6070um x 1380um (exclude scribe line) Die Thickness: 670 +/-25um Bump Size PAD: 1-63 52 ...
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... Table 2 - SSD1800Z Gold Bump Die Pad Coordinates PAD# NAME 1 -2401. DVSS -2325. -2248.93 4 DVDD -2172.63 5 -2096. -2020. -1943. -1867. -1791. -1714. -1638. -1562. -1485. -1409.63 15 DVDD -1333.33 16 AVDD -1257.03 ...
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... SEG42 -159.25 125 SEG43 -222.95 126 SEG44 -286.65 127 SEG45 -350.35 128 SEG46 -414.05 129 SEG47 -477.75 130 SEG48 -541.45 SSD1800 Series Rev 1 PAD# NAME 593.43 131 SEG49 593.43 132 SEG50 593.43 133 SEG51 593.43 134 SEG52 593.43 135 SEG53 593 ...
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... PIN ARRANGEMENT OF SSD1800AV BARE DIE Figure 3 - SSD1800AV Pin Arrangement Die Size: 6260um x 1810um (include scribe line) Die Thickness: 670 +/-25um Pad Metal Size 88um Pad Opening Size 80um Pad number PADS: 1-9, 48-56, 72-80, 119-127 PADS: 57, 58, 70, 71, 128, 129, 141, 142 ...
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... Table 3 - SSD1800AV Bare Die Pad Coordinates PAD # NAME -2748.20 -772. -2638.13 -772.71 3 COM15 -2528.05 -772.71 4 COM14 -2417.98 -772.71 5 COM13 -2307.90 -772.71 6 COM12 -2197.83 -772.71 7 COM11 -2087.75 -772.71 8 COM10 -1977.68 -772.71 9 COM9 -1867.60 -772.71 10 COM8 -1757.53 -772. -1662.68 -772 ...
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... pins must be fixed to high or low in 4-bit bus mode. After resets, SSD1800 is the serial data input (SDA) and D 7 Mar 2004 -D is treated as display data the serial clock input (SCK) ...
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... This pin is to select the data length for parallel data input. = Low When Low or High: serial interface mode = High When Low: 4-bit bus mode DL = High: 8-bit bus mode This pin must be fixed to high or low in serial mode. SSD1800 Series Rev 1.0 P 13/42 Mar 2004 and R , are connected between and V , and V ...
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... These pins provide the LCD segment driving signals. Their output voltage levels are AV standby mode. 7.21 NC These are the No Connection pins. Nothing should be connected to these pins, nor they are connected together. These pins should be left open individually. Solomon Systech during sleep mode and SS SSD1800 Series Mar 2004 P 14/42 Rev 1.0 ...
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... Oscillator Circuit This module is an On-Chip low power RC oscillator circuitry. The oscillator generates the clock for the DC-DC voltage converter. This clock is also used in the Display Timing Generator. SSD1800 Series Rev 1.0 P 15/42 Mar 2004 -D is interpreted as a Command and it will be decoded and be written to ...
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... ADDRESS COUNTER (AC) Address Counter (AC) in SSD1800 stores DDRAM/ CGRAM/ ICONRAM address. After writing into or reading from DDRAM/ CGRAM/ ICONRAM automatically increased by 1. There is only one address counter and stores the address among DDRAM / CGRAM / ICONRAM. DL C68/80 CS D/C R/W (WR) E(RD Figure 4 - Timing Diagram of 8-bit Parallel Bus Mode Data Transfer (6800 MPU Mode) ...
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... Figure 6 - Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (6800 MPU Mode) DL C68/80 CS D/C R/W (WR) E(RD Figure 7 - Timing Diagram of 4-bit Parallel Bus Mode Data Transfer (8080 MPU Mode) CS SDA(D7) SCK(D6) D/C Figure 8 – Timing Diagram of Serial Data Transfer SSD1800 Series Rev 1.0 P 17/42 Mar 2004 Lower Upper 4-bits 4-bits Write Instruction NOP Dummy Read Upper Lower ...
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... SEG S11 S12 S13 S14 … … … … S66 S67 S68 S69 S71 S72 S73 S74 S76 S77 S78 S79 SSD1800 Series P 18/42 Rev 1.0 ...
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... Note: The CGROM 0000xxxx are empty. SSD1800 Series Rev 1.0 P 19/42 Mar 2004 Table 5 - CGROM Character Code Solomon Systech ...
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... SSD1800 Series ...
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... LCD driving voltage with internal voltage reference, VREF, relative to AVSS AVDD AVDD SSD1800 AVDD + C1P + C2 C2 C1N C2P + C2 C2N VL6 3x DC-DC Converter 2x DC-DC Converter Remarks 2.2µF - 4.7µ 0.1µF - 1µF Figure 10 – Configurations for DC-DC Converter SSD1800 Series Rev 1.0 P 21/42 Mar 2004 ICONRAM bits ...
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... A low power consumption circuit design Mar 2004 SS n VL6 Contrast Maximum High Minimum Low (“ - “: Don’t care) SSD1800 Series P 22/42 Rev 1.0 and ...
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... The 1st line of display is the address 00h-0Fh. 8.14 Display Data Latch A series of registers carrying the display signal information. For SSD1800, there are 105 latches (80 + 25) for holding the data, which will be fed to the HV Buffer Cell and Level Selector to output the required voltage levels. ...
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... AVDD C1P + C2 C1N + C2P VL6 VF VL6 VL5 VL4 VL3 VL2 AVSS GND VDD AVDD C1P C1N C2P C2N VF E xte rn al VL6 VL5 S up ply VL4 VL3 VL2 AVSS GND ( All Capacitor is C2 0.1 uF SSD1800 Series P 24/42 Rev 1.0 ...
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... FRAME FREQUENCY 1/17 Duty SSD1800 Series Rev 1.0 P 25/42 Mar 2004 Solomon Systech ...
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... cursor on DDRAM/ CGRAM address range: DDRAM: 00h - 3Fh CGRAM: 40h - 7Fh ICONRAM address range / Contrast Control Register: ICONRAM: 00h - 0Fh Contrast Control Register: 10h TE: 11h (test byte) Command for No Operation Reserved for IC testing. Do Not use Mar 2004 P 26/42 Rev 1.0 SSD1800 Series ...
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... To write data to the internal memories (DDRAM/ CGRAM/ ICONRAM), input low to R pin and high pin for 6800-series and 8080-series parallel mode. For serial interface, it will always be in write mode. Address counter will be increased by one automatically after each data write. SSD1800 Series Rev 1.0 P 27/42 Mar 2004 ...
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... COM signal, the last character line will not be displayed. It will happen at following case: 1. For 01, where COM0-COM15 is double height The 2nd line will not be displayed. Figure 14– Function set command (X Figure 15 - COM0 ~ COM15 is a Double Height Line in function set command (X Solomon Systech SSD1800 Series Mar 2004 P 28/42 Rev 1.0 = 01) ...
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... LCD alternate between inverting display character and normal display character at the cursor position with about a half second. On the contrary, if cursor control bit is low, only a normal character is displayed regardless of blink control bit. SSD1800 Series Rev 1.0 P 29/42 Mar 2004 ...
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... Display State (Cursor Mode (Blinking Mode Solomon Systech Figure 16 - Display Attributes Mar 2004 SSD1800 Series P 30/42 Rev 1.0 ...
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... DDRAM LINE 2 (10H - 1FH) 20H DDRAM LINE 3 (20H - 2FH) 30H DDRAM LINE 4 (30H - 3FH) 40H CGRAM (PATTERN 0) 50H CGRAM (PATTERN 2) 60H CGRAM (PATTERN 4) 70H CGRAM (PATTERN 6) SSD1800 Series Rev 1.0 P 31/42 Mar 2004 CGRAM (PATTERN 1) CGRAM (PATTERN 3) CGRAM (PATTERN 5) ...
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... This command forces the driver chip into its test mode for internal testing of the chip. Under normal operation, user should NOT use this command. Solomon Systech Table 10 - ICONRAM Address Mapping Reserved E Mar 2004 SSD1800 Series P 32/42 Rev 1.0 ...
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... Reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (e.g., either Unused outputs must be left open. This device may be light sensitive. Caution ss DD should be taken to avoid exposure of this device to any light source during normal operation. This device is not radiation protected. SSD1800 Series Rev 1.0 P 33/42 Mar 2004 Value Unit -0.3 to +4.0V V -0.3 to +6.5V ...
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... Typ Max 2.7 3 500 - - 5 - 5.8 - 5.8 - DVDD - 0.2*DVDD - - - - 0.4 - 5.8 - Floating - - (a-1)/ (a-2 7.5 2 2.06 SSD1800 Series P 34/42 Rev 1.0 Unit V µA µA µ µA µA µA µ ...
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... Low Pulse Width (write High Pulse Width (read High Pulse Width (write) t Rise Time R t Fall Time F Figure 17– 6800-series MCU Parallel Interface Waveform SSD1800 Series Rev 1.0 P 35/42 Mar 2004 Test Condition Min Internal Oscillator 67.5 ° 3V ...
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... High Pulse Width (write) t Rise Time R t Fall Time F Figure 18– 8080-series MCU Parallel Interface Waveform Solomon Systech Min Typ 650 - 100 - 450 - 450 - 150 - 150 - - - - - SSD1800 Series Mar 2004 P 36/42 Rev 1.0 Max Unit - 100 ...
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... Write Data Setup Time DSW t Write Data Hold Time DHW t Clock Low Time CLKL t Clock High Time CLKH t Rise Time R t Fall Time F Figure 19– Serial Interface Characteristics SSD1800 Series Rev 1.0 P 37/42 Mar 2004 Min Typ Max Unit 1000 - - 300 - - ns 150 ...
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... SEG0…………………………………………………………SEG79 SSD1800 IC 16 MUX (DIE FACE IP) DVDD VL2 VL3 VL4 VL5 VL6 AVDD VDD=3.0V Mar 2004 COMI0 COM0 COM1 : .. . . . . : COM6 COM7 COM7 COM6 COM5 : : . . COM0 COMI0 0.1uF + External Power Supply AVSS SSD1800 Series P 38/42 Rev 1.0 ...
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... Pins connected to DVss: REF, CLK R E(/RD), C68 D5-D0 Figure 21 - Application Circuit: ALL internal power mode with 2x regulated DC-DC converter SSD1800 Series Rev 1.0 P 39/42 Mar 2004 DISPLAY PANEL SIZE ICON LINE SSD1800 IC 16 MUX (DIE FACE IP) VL6 C1N C1P C2P DVDD VL2 VL3 VL4 VL5 VL6 AVDD +C1 ...
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... VL6 C1N C1P C2N C2P DVDD VL2 VL3 VL4 VL5 VL6 AVDD + C1: 2.2 -4.7 uF AVDD C2: 0.1-1uF VDD = 3.0V (8-bit 8080 mode) Mar 2004 COMI0 COM0 COM1 : : . . COM6 COM7 COM7 COM6 COM5 : : COM0 COMI0 AVSS Remarks: R1 and R2 = 500K-2.5M ohms SSD1800 Series P 40/42 Rev 1.0 ...
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... Data Input 6. Data writing (RAM clear) (DDRAM=20h, CG/ICONRAM=00h) Command Input 7. Display control (turns on the display) (There is an auto mask off period ~ 260ms) End of initialization Figure 23- Recommended INITIALIZING of SSD1800 SSD1800 Series Rev 1.0 P 41/42 Mar 2004 NOTE: At instructions 1-6, the minimum clock cycle Power On SS time is 650ns for PPI. For details, pls refer to the SSD1800 datasheet “ ...
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... Solomon Systech was negligent regarding the design or manufacture of the part. http://www.solomon-systech.com Solomon Systech SSD1800 Series Mar 2004 P 42/42 Rev 1.0 ...