PLL202-16 PhaseLink (PLL), PLL202-16 Datasheet - Page 10
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PLL202-16
Manufacturer Part Number
PLL202-16
Description
Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST
Manufacturer
PhaseLink (PLL)
Datasheet
1.PLL202-16.pdf
(16 pages)
Note: *: Default value at power-up
Note: This register will be initialized to 0 following WATCHDOG RESET
Note: *: Default value at power-up.
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
0
0
1
1
0*
0*
0*
0*
0*
0*
0*
0*
0
0
0
0
0
0
0
1
WDT Fall-back Frequency selection for FS4
WDT Fall-back Frequency selection for FS3
WDT Fall-back Frequency selection for FS2
WDT Fall-back Frequency selection for FS1
WDT Fall-back Frequency selection for FS0
Vendor ID Bit 2*
Vendor ID Bit 1*
Vendor ID Bit 0*
Linear programming sign bit ( 0 is “ ”, 1 is “ ” )
Linear programming magnitude bit 6 (MSB)
Linear programming magnitude bit 5
Linear programming magnitude bit 4
Linear programming magnitude bit 3
Linear programming magnitude bit 2
Linear programming magnitude bit 1
Linear programming magnitude bit 0 (LSB)
Watchdog Timer Enable Bit. 1=Enable, 0=Disable
Device ID Bit 6*
Watchdog Time Interval Bit 5 (MSB)
Watchdog Time Interval Bit 4
Watchdog Time Interval Bit 3
Watchdog Time Interval Bit 2
Watchdog Time Interval Bit 1
Watchdog Time Interval Bit 0 (LSB)
Rev 07/10/01 Page 10
Device ID Bit 5*
Device ID Bit 4*
Device ID Bit 3*
Device ID Bit 2*
Device ID Bit 1*
Device ID Bit 0*
Revision ID Bit3*
Revision ID Bit2*
Revision ID Bit1*
Revision ID Bit0*
Vendor ID Bit 3*