PLL202-16 PhaseLink (PLL), PLL202-16 Datasheet - Page 11

• Manufacturer Part Number: PLL202-16
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST
• Manufacturer: PhaseLink (PLL)

To simplify traditional loop counter setting, the PLL202-16 device incorporates SMART-BYTE ™
technology with a single byte programming via I2C. Detail of PLL202-16's dual mode frequency
programming method is described below:
1. ROM-table Frequency Programming:
2. Micro-step Linear Frequency Programming:
1. Procedures to program target CPU frequency to 108 Mhz:
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
The pre-defined 32 frequencies found in Frequency table can be accessed through 3 external jumpers.
CPU Frequency can be programmed via I2C in fine and linear positive or negative stepping around
selected CPU frequency in Frequency table. The highest step is either +127 or -127. Other bus
frequencies will be changed proportionally with the rate that CPU frequency changes. The formula is
as follow:
A. Locate the closest CPU frequency from Frequency-ROM table: 107
B.
C. Solve M (Linear Magnitude factor) in integer:
D. Program I2C register:
= 0.22
F
F
Sign M6 M5 M4 M3 M2 M1 M0
7
0 0 0 0 0 1 0 0
CPU
PCI
M = (F
6
= 107 + (0.22) * 4
= 35.67 * (1 + 0.822 %)
= (108 - 107) / 0.22
= 4
5
Where:
CPU
4
- F
3
CPU
-
1. M is magnitude factor defined in I2C Byte 7.bit (0:6)
2.
3.
2
ROMTABLE
1

      

(sign bit) of M is defined in I2C Byte7.bit 7
is a constant equal to 0.22.
F
0
) /
= 107.88 (% of frequency increased vs. ROM Table = 0.822 % )
CPU
= 35.96
Setting of M = +4 in I2C.BYTE 7
=
F
CPU.ROM-Table
*
M


Rev 07/10/01 Page 11