PLL202-16 PhaseLink (PLL), PLL202-16 Datasheet - Page 2

• Manufacturer Part Number: PLL202-16
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST
• Manufacturer: PhaseLink (PLL)

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MULT_SEL1/PCI1
SEL24_48/REF
FS2/24_48MHz
CPU_STOP#
WDRESET#
PCI_STOP#
Vtt_PWRG#
FS3/48MHz
FS0/PCI_F
FS1/PCI0
AGP(0:2)
PCI(2:7)
SDATA
Name
XOUT
SCLK
PD#
XIN
14,15,17,
Number
18,19,21
23,26,27
29
31
10
11
12
22
28
30
32
33
1
4
5
7
8

      

Type
O
O
O
B
B
B
B
B
B
B
O
I
I
I
I
I
I
Bi-directional pin. At power-up, the SEL24_48 input value is sensed and
internally latched. 0 = 24MHz, 1 = 48MHz. After power-up, the pin acts
as 3.3V REF 14.318MHz output (2x drive strength). This pin has a
100k
14.318Mhz crystal input to be connected to one end of the crystal.
14.318Mhz crystal output.
Bi-directional pin. At power-up, the FS3 input value is sensed and
internally latched. After power-up, the pin acts as fixed 48MHz output.
This pin has a 100k
Bi-directional pin. At power-up, the FS2 input value is sensed and
internally latched. After power-up, the pin acts as fixed 48 or 24MHz
output (I2C selectable). This pin has a 100k
Bi-directional pin. At power-up, the FS0 input value is sensed and
internally latched. After power-up, the pin acts as PCI_F output. This pin
has a 100k
Bi-directional pin. At power-up, the FS1 input value is sensed and
internally latched. After power-up, the pin acts as PCI1 output. This pin
has a 100k
Bi-directional pin. At power-up, the MULT_SEL1 input value is sensed
and internally latched. After power-up, the pin acts as PCI1 output.
MULT_SEL1 is used to define the current multiplier of the CPU clock
outputs. 0 selects Ioh = 4 x IREF, 1 selects Ioh = 6 x IREF. This pin has
a 100k
PCI clock outputs.
Power Down Control input. When low, Power Down will disable all clock
outputs including internal VCO and crystal clock. This pin has a 100k
internal pull-up.
AGP clock outputs.
Serial data input for serial interface port.
Watchdog timer reset signal.
Halts PCI clocks when low (except PCI_F which is free running). This pin
has a 100k
Halts CPU clocks when input low. This pin has a 100k
This 3.3V LVTTL input is a level sensitive strobe used to determine
when FS (0:3) and MULT_SEL1 inputs are valid and ready to be
sampled (active low).
internal pull-down.
internal pull-up.
internal pull-up.
internal pull-down.
internal pull-up.
internal pull-down.
Description


internal pull-down.
Rev 07/10/01 Page 2
internal pull-up