PLL202-16 PhaseLink (PLL), PLL202-16 Datasheet - Page 3
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PLL202-16
Manufacturer Part Number
PLL202-16
Description
Ali, Via, Sis, Intel 440BX Chipset FTGS , Freq. Progr., Power Mgt, Wdt, Drive Ctrl, SST
Manufacturer
PhaseLink (PLL)
Datasheet
1.PLL202-16.pdf
(16 pages)
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
MULT_SEL1
VDD_CPU_CS
CPUC(0:1)
VDD_APIC
CPUT(0:1)
CPUT_CS
CPUC_CS
APIC(0:1)
IREF
GND
VDD
0
1
Board target trace (Z)
2,6,16,24,38,48
25,36,44,47
3,9,13,20,
35,40
34,39
45,46
50
50
37
42
41
43
48
O
O
O
O
O
P
P
P
P
I
Reference R (Rr); IREF = VDD/(3*Rr)
True clock of differential pair of CPU outputs.
Complementary clock of differential pair of CPU outputs.
This pin establishes the reference current for the CPU pairs, it requires a
fixed precision resistor tied to ground in order to establish the
appropriate current.
True CPU output for the Chipset (2.5V push-pull output).
Complementary CPU output for the Chipset (2.5V push-pull output).
APIC clock outputs running at half of PCI output frequency.
3.3V Power Supply.
2.5V Power Supply for CPUT_CS and CPUC_CS outputs.
2.5V Power Supply for APIC outputs.
Ground (0.0V) connector.
Rr = 221
Rr = 475
(1%); IREF = 5.00mA
(1%); IREF = 2.32mA
Output Current
Ioh = 4 x IREF
Ioh = 6 x IREF
Rev 07/10/01 Page 3
0.7V @ 50
1.0V @ 50
Voh @ Z