gl850g Genesys Logic, gl850g Datasheet

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gl850g

Manufacturer Part Number
gl850g
Description
Gl850g Usb 2.0 Low-power Hub Controller
Manufacturer
Genesys Logic
Datasheet

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Genesys Logic, Inc.
GL850G
USB 2.0
HUB Controller
Datasheet
Revision 1.05
Mar. 10, 2008

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gl850g Summary of contents

Page 1

... Genesys Logic, Inc. GL850G USB 2.0 HUB Controller Datasheet Revision 1.05 Mar. 10, 2008 ...

Page 2

... All trademarks are the properties of their respective owners. Office: Genesys Logic, Inc. 12F, No. 205, Sec. 3, Beishin Rd., Shindian City, Taipei, Taiwan Tel: (886-2) 8913-1888 Fax: (886-2) 6629-6168 http://www.genesyslogic.com ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Page 2 ...

Page 3

... Modify Table 6.1-Maximum Ratings, P.21 1.04 08/08/2007 Modify Table 6.6-DC Supply Current, P.23 1.05 03/10/2008 ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Revision History Description 1. Add SSOP-28 Package Assignment ,Ch3, P.11~14 2. Add low/high-enabled power switches, Ch5.2.7, P.23 3. Add built- 3.3V power regulator, Ch5.2.5, P.21 4 ...

Page 4

... ONFIGURATION AND CHAPTER 6 ELECTRICAL CHARACTERISTICS............................... 24 6 AXIMUM ATINGS 6 PERATING ANGES 6 HARACTERISTICS 6 OWER ONSUMPTION CHAPTER 7 PACKAGE DIMENSION..................................................... 27 CHAPTER 8 ORDERING INFORMATION ............................................ 29 ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller TABLE OF CONTENTS ................................................................................... 12 I/O S ....................................................... 18 ETTINGS ................................................................................. 24 ................................................................................ 24 ............................................................................ 24 ............................................................................ 25 Page 4 ...

Page 5

... F 3.1- - - - GL850G 48 P IGURE F 3.2- - - - GL850G 28 P IGURE F 4.1 – GL850G B IGURE F 5.1 – O IGURE PERATING IN F 5.2 – O IGURE PERATING IN F 5.3 – P IGURE OWER ON RESET DIAGRAM F 5.4 – P IGURE OWER ON SEQUENCE OF F 5.5 – T IGURE IMING OF F 5.6 – I IGURE ...

Page 6

... T 3.1- - - - GL850G 48 P ABLE T 3.2- - - - GL850G 28 P ABLE T 3 ABLE IN ESCRIPTIONS T 5.1 – 93C46 C ABLE ONFIGURATION T 6.1 – M ABLE AXIMUM T 6.2 – O ABLE PERATING T 6.3 – ABLE HARACTERISTICS T 6.4 – ABLE HARACTERISTICS OF T 6.5 – ABLE HARACTERISTICS OF T 6.6 – ...

Page 7

... Chapter 5). Each downstream port of GL850G supports two-color (green/amber) status LEDs to indicate normal/abnormal status. GL850G also support both Individual and Gang modes (4 ports as a group) for power management. The GL850G is a full function solution which supports both Individual/Gang power management modes and the two-color (green/amber) status LEDs ...

Page 8

... Available in 48-pin LQFP and 28-pin SSOP package (Full Function only available in 48-pin) • Number of Downstream port can be configured by GPIO without external EEPROM. • Applications: − Stand-alone USB hub PC motherboard USB hub, Docking of notebook − ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Page 8 ...

Page 9

... Gaming console LCD monitor hub − Any compound device to support USB HUB function − ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Page 9 ...

Page 10

... CHAPTER 3 PIN ASSIGNMENT 3.1 Pinouts Figure 3.1 ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller GL850G - - - - G L850G 48 Pin LQFP Pinout Diagram Page 10 ...

Page 11

... P 9 DM2 B 10 DP2 B 11 RREF B 12 AVDD P ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller - - - - G L850G 28 Pin SSOP Pinout Diagram Table 3.1 - - - - G L850G 48 Pin List 13 AGND P 25 DVDD ...

Page 12

... Note: USB signals must be carefully handled in PCB routing. For detailed information, please refer to GL850G Design Guideline. GL850G Pin Name 48Pin# 42,40, OVCUR1~4# 30,28 43,41, PWREN1~4# 31,29 ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Table 3.2 - - - - G L850G 28 Pin List 8 DM3 B 15 GND 9 DP3 B 16 DVDD 10 AVDD P ...

Page 13

... This pin is default put in input mode after power-on strapped during this period. After the strapping period, this pin will be set to output mode, and then output high for normal mode. When GL850G is suspended, this pin will 18 B output low. *For detailed explanation, please see Chapter 5 ...

Page 14

... DVDD 38,44 GND -- V5 47 V33 48 Note: Analog circuits are quite sensitive to power and ground noise. PCB layout must take care the power routing and the ground plane. For detailed information, please refer to GL850G Design Guideline. Notation: Type O Output I Input I_5V 5V tolerant input ...

Page 15

... CHAPTER 4 BLOCK DIAGRAM Figure 4.1 – GL850G Block Diagram (single TT) ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Page 15 ...

Page 16

... The functionality of FRTIMER is described in section 11.2 of USB Specification Revision 2.0. 5.1.4 µ the micro-processor unit of GL850G 8-bit RISC processor with 2K ROM and 64 bytes RAM. It operates at 6MIPS of 12Mhz clock to decode the USB command issued from host and then prepares the data to respond to the host. In addition, C can handle GPIO (general purpose I/O) settings and reading content of EEPROM to support high flexibility for customers of different configurations of hub ...

Page 17

... TT implements the control logic defined in section 11.14 ~ 11.22 of USB specification Revision 2.0. TT basically handles the unbalanced traffic speed between the USPORT (operating in HS) and DSPORTS (operating in FS/LS) of hub. GL850G adopts the single TT architecture to provide the most cost effective solution. Single TT shares the same buffer control module for each downstream port. GL852 adopts multiple TT architecture to provide the most performance effective solution ...

Page 18

... The power on sequence will start after the power good voltage has been met, and the reset will be released after approximately 2.7 nS after power good. ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller USB2.0 HOST/HUB REPEATER ...

Page 19

... Figure 5.4 – Power on sequence of GL850G 5.2.2 PGANG/SUSPND Setting To save pin count, GL850G uses the same pin to decide individual/gang mode as well as to output the suspend flag. The individual/gang mode is decided within 20us after power on reset. Then, about 50ms later, this pin is changed to output mode. GL850G outputs the suspend flag once it is globally suspended. For ...

Page 20

... SELF/BUS Power Setting GL850G can operate under bus power and conform to the power consumption limitation completely (suspend current < 2.5 mA, normal operation current < 100 mA). By setting PSELF, GL850G can be configured as a bus-power or a self-power hub. ©2000-2008 Genesys Logic Inc. - All rights reserved. ...

Page 21

... Power Self 0: Power Bus 5.2.4 LED Connections GL850G controls the LED lighting according to the flow defined in section 11.5.3 of Universal Serial Bus Specification Revision2.0 . Both manual mode and Automatic mode are supported in GL850G. When GL850G is globally suspended, GL850G will turn off the LED to save power. ...

Page 22

... SERIAL NUMBER LENGTH: offset 70h contains the value of serial number string. Values of serial number string is contained after offset 71h. The schematics between GL850G and 93C46 is depicted in the following figures: ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Table 5.1 – ...

Page 23

... Figure 5.9 – Schematics Between GL850G and 93C46 GL850G firstly verifies the check sum after power on reset. If the check sum is correct, GL850G will take the configuration of 93C46 as part of the descriptor contents. To prevent the content of 93C46 from being over-written, amber LED will be disabled when 93C46 exists. ...

Page 24

... HIGH level output voltage when Pad internal pull down resister DN R Pad internal pull up resister UP ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Table 6.1 – Maximum Ratings Parameter Table 6.2 – Operating Ranges Parameter Parameter =8mA OL =8mA OH Min ...

Page 25

... Driver output resistance for USB 2.0 HS DRV 6.4 Power Consumption Symbol Active ports I SUSP ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Parameter of 1. 15K to GND ) L Parameter of 1. Table 6.6 – DC Supply Current Condition Host Device Suspend ...

Page 26

... No Active *1: F: Full-Speed, H: High-Speed ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller n/a H n/a 120 mA 102 Page 26 ...

Page 27

... CHAPTER 7 PACKAGE DIMENSION Figure 7.1 – GL850G 48 Pin LQFP Package ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller GL850G AAAAAAAGAA YWWXXXXXXXX Page 27 ...

Page 28

... Figure 7.2 – GL850G 28 Pin SSOP Package ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Page 28 ...

Page 29

... Part Number GL850G-MNNXX 48-pin LQFP GL850G-MNGXX 48-pin LQFP GL850G-HHNXX 28-pin SSOP GL850G-HHGXX 28-pin SSOP ©2000-2008 Genesys Logic Inc. - All rights reserved. GL850G USB 2.0 Low-Power HUB Controller Table 8.1 – Ordering Information Package Normal/Green Normal Package Green Package Normal Package Green Package Version Status ...

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