gl850g Genesys Logic, gl850g Datasheet - Page 8

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gl850g

Manufacturer Part Number
gl850g
Description
Gl850g Usb 2.0 Low-power Hub Controller
Manufacturer
Genesys Logic
Datasheet

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CHAPTER 2 FEATURES
©2000-2008 Genesys Logic Inc. - All rights reserved.
USB specification Revision 2.0 (Not supported on SSOP 28 package)
downstream ports (Individual mode is not supported on SSOP 28 package)
Compliant to USB specification Revision 2.0
On-chip 8-bit micro-processor
Single Transaction Translator (STT)
Integrate USB 2.0 transceiver
Each downstream port supports two-color status indicator, with automatic and manual modes compliant to
Built-in upstream 1.5K pull-up and downstream 15K pull-down
Embed serial resister for USB signals
Support both individual and gang modes of power management and over-current detection for
Power enable pin supports both low/high-enabled power switches.
Conform to bus power requirements
Automatic switching between self-powered and bus-powered modes
Support compound-device (non-removable in downstream ports) by I/O pin configuration
Configurable non-removable device support
Built-in PLL supports external 12 MHz crystal / Oscillator clock input
Built-in 5V to 3.3V regulator
Low power consumption
Improve output drivers with slew-rate control for EMI reduction
Internal power-fail detection for ESD recovery
Available in 48-pin LQFP and 28-pin SSOP package (Full Function only available in 48-pin)
Number of Downstream port can be configured by GPIO without external EEPROM.
Applications:
Support 4/3/2 downstream ports by I/O pin configuration
Upstream port supports both high-speed (HS) and full-speed (FS) traffic
Downstream ports support HS, FS, and low-speed (LS) traffic
1 control pipe (endpoint 0, 64-byte data payload) and 1 interrupt pipe (endpoint 1, 1-byte data payload)
Backward compatible to USB specification Revision 1.1
RISC-like architecture
USB optimized instruction set
Performance: 6 MIPS @ 12MHz
With 64-byte RAM and 2K mask ROM
Support customized PID, VID by reading external EEPROM
Support downstream port configuration by reading external EEPROM
Single TT shares the same TT control logics for all downstream port devices. This is the most cost
effective solution for TT. Multiple TT provides individual TT control logics for each downstream port.
This is a performance better choice for USB 2.0 hub. Please refer to GL852 datasheet for more
detailed information.
Stand-alone USB hub
PC motherboard USB hub, Docking of notebook
GL850G USB 2.0 Low-Power HUB Controller
Page 8

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