PLL602-10 PhaseLink (PLL), PLL602-10 Datasheet

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PLL602-10

Manufacturer Part Number
PLL602-10
Description
, 12 - 24MHz In, 96 - 400MHz Out, CMOS, Pecl, LVDS
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTIONS
The PLL602-10 is a monolithic low jitter and low
phase noise (-134dBc/Hz @ 10kHz offset) XO IC
Die, with CMOS, LVDS and PECL output, for 96MHz
to 400MHz output range, using a low frequency
crystal.
The same die can be used as a XO with output
frequencies ranging from F
to selector pads allowing bonding options (see
Divider Selection Table on this page). This makes
the PLL602-10 ideal for a wide range of applications.
DIE SPECIFICATIONS
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
SELECT
Pad dimensions
Low phase noise output for the 96MHz to
400MHz range (-134 dBc at 10kHz offset).
Selectable CMOS, PECL and LVDS output.
12 to 25MHz crystal input.
Output Enable selector.
3.3V operation.
Available in DIE (65 mil x 62 mil).
Reverse side
Thickness
XOUT
XIN
Name
Size
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
Reference
Divider
XTAL
OSC
Comparator
80 micron x 80 micron
Divider
Phase
VCO
XIN
x 8 to F
62 x 65 mil
Value
10 mil
GND
Charge
Pump
XIN
x 16 thanks
Loop
Filter
VCO
OE
DIE CONFIGURATION
MULTIPLIER SELECTION
Note: Selector pad defaults to ‘1’, wire bond to GND to set to ‘0’
OUTPUT SELECTION AND ENABLE
OUTSEL1
Y
Pad #18
Pad #19
X
0
0
1
1
OE (Pad #30)
CLKBAR
CLK
(0,0)
0
1
1 (Default)
26
27
28
29
30
31
25
0
1
OUTSEL0
Pad #25
24
2
Preliminary
0
1
0
1
23
MULTIPLIER
3
F
F
22
XIN
4
XIN
21
x 16
65 mil
5
x 8
High Drive CMOS
Standard CMOS
PECL
LVDS
Tri-state
Output enabled
20
6
PLL602-10
Selected Output
19
7
OUTPUT RANGE
18
192 – 400 MHz
State
8
96 – 200 MHz
Rev 11/06/02 Page 1
12
10
16
15
14
13
11
17
9
(1550,1475)

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PLL602-10 Summary of contents

Page 1

... Output Enable selector. 3.3V operation. Available in DIE (65 mil x 62 mil). DESCRIPTIONS The PLL602- monolithic low jitter and low phase noise (-134dBc/Hz @ 10kHz offset Die, with CMOS, LVDS and PECL output, for 96MHz to 400MHz output range, using a low frequency crystal. ...

Page 2

... PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Recommended ESR 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 SYMBOL SYMBOL CONDITIONS Parallel Fundamental F XIN Mode C (xtal cut R E PLL602-10 Preliminary MIN. MAX 0 ...

Page 3

... Vdd – 1.3V (PECL) CONDITIONS With capacitive decoupling between VDD and GND. With capacitive decoupling between VDD and GND. Over 10,000 cycles. 155MHz @100Hz offset 155MHz @1kHz offset 155MHz @10kHz offset 155MHz @100kHz offset PLL602-10 Preliminary MIN. TYP. MAX. 80/60/35 3.13 3. ...

Page 4

... I OSD SYMBOL CONDITIONS R = 100 (see figure LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80 DIFF 20 PLL602-10 Preliminary MIN. TYP. MAX. 247 355 454 -50 50 1.4 1.6 0.9 1.1 1.125 1.2 1.375 -5.7 -8 MIN. TYP. MAX. 0.2 0.7 1.0 0.2 0.7 1.0 LVDS Switching Test Circuit ...

Page 5

... V OL SYMBOL CONDITIONS @20/80% - PECL t r @80/20% - PECL t f PECL Output Skew VDD OUT 2.0V 50% OUT PECL Transistion Time Waveform DUTY CYCLE PLL602-10 Preliminary MIN. MAX. V – 1.025 DD V – 1.620 DD MIN. TYP. MAX. 0.6 1.5 0.5 1.5 t SKEW Rev 11/06/02 Page 5 UNITS V V UNITS ...

Page 6

... PLL602-10 Preliminary Rev 11/06/02 Page 6 ...

Page 7

... LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL602- PLL602-10 Preliminary TEMPERATURATRE C=COMMERCIAL M=MILITARY ...

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