PLL602-10 PhaseLink (PLL), PLL602-10 Datasheet - Page 3
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PLL602-10
Manufacturer Part Number
PLL602-10
Description
, 12 - 24MHz In, 96 - 400MHz Out, CMOS, Pecl, LVDS
Manufacturer
PhaseLink (PLL)
Datasheet
1.PLL602-10.pdf
(7 pages)
3. General Electrical Specifications
4. Jitter and Phase Noise specification
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Supply Current, Dynamic
(with Loaded Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
Period jitter RMS
Accumulated jitter RMS
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
Phase Noise relative to carrier
PARAMETERS
96MHz – 400MHz Low Phase Noise XO (for 12 – 25MHz Crystals)
PARAMETERS
SYMBOL
V
I
DD
DD
With capacitive decoupling
between VDD and GND.
With capacitive decoupling
between VDD and GND. Over
10,000 cycles.
155MHz @100Hz offset
155MHz @1kHz offset
155MHz @10kHz offset
155MHz @100kHz offset
PECL/LVDS/CMOS
@ 1.4V (CMOS)
@ 1.25V (LVDS)
@ Vdd – 1.3V (PECL)
CONDITIONS
CONDITIONS
MIN.
MIN.
Preliminary
3.13
45
45
45
TYP.
-114
-134
-134
-90
11
7
TYP.
50
50
50
50
PLL602-10
MAX.
80/60/35
Rev 11/06/02 Page 3
MAX.
3.47
55
55
55
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
UNITS
ps
ps
UNITS
mA
mA
%
V