PLL602-11 PhaseLink (PLL), PLL602-11 Datasheet

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PLL602-11

Manufacturer Part Number
PLL602-11
Description
, 12 - 24MHz In, 96 - 200MHz Out, Pecl, 3.3V
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTION
The PLL602-11 is a monolithic low jitter and low
phase noise (-134dBc/Hz @ 10kHz offset) XO IC
with PECL output, for 96MHz to 192MHz output
range. It provides a low phase noise reference
frequency using a low cost crystal.
The chip delivers an output frequency of F
This makes the PLL602-11 ideal for a wide range of
applications, including 155.52MHz for SONET.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
Low phase noise output for the 96MHz to
192MHz range (-134 dBc at 10kHz offset).
PECL output.
12 to 24MHz crystal input.
Integrated crystal load capacitor: no external
load capacitor required.
Output Enable selector.
3.3V operation.
Available in 16 Pin TSSOP or SOIC.
XOUT
96MHz – 192MHz Low Phase Noise PECL XO (12 – 24MHz Crystals)
XIN
Reference
Divider
XTAL
OSC
Comparator
Divider
Phase
VCO
Charge
Pump
XIN
Loop
Filter
x 8.
VCO
OE
PIN CONFIGURATION
CLKBAR
CLK
OE (Pin 5)
1 (Default)
XOUT
0
GND
GND
VDD
VDD
N/C
XIN
OE
Preliminary
1
2
3
4
5
6
7
8
F
OUT
Tri-state
Output enabled
= F
XIN
PLL602-11
x 8
Output State
16
15
14
13
12
11
10
9
Rev 07/17/01 Page 1
VDD
GND_BUF
CLKBAR
VDD_BUF
CLK
GND_BUF
GND
GND

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PLL602-11 Summary of contents

Page 1

... PECL output, for 96MHz to 192MHz output range. It provides a low phase noise reference frequency using a low cost crystal. The chip delivers an output frequency of F This makes the PLL602-11 ideal for a wide range of applications, including 155.52MHz for SONET. BLOCK DIAGRAM VCO Divider ...

Page 2

... Not connected. P GND Power connectors. P GND connector for output buffers. O True clock output pin. P +3.3V Power supply connector for output buffers. O Complementary clock output pin. SYMBOL PLL602-11 Preliminary Description MIN. MAX 0 0.5 V 0.5 ...

Page 3

... Vdd – 1.3V (PECL) CONDITIONS With capacitive decoupling between VDD and GND. With capacitive decoupling between VDD and GND. Over 10,000 cycles. 155MHz @100Hz offset 155MHz @1kHz offset 155MHz @10kHz offset 155MHz @100kHz offset PLL602-11 Preliminary MIN. TYP. MAX. UNITS 12 24 TBD 30 MIN. ...

Page 4

... V OL SYMBOL CONDITIONS @20/80% - PECL t r @80/20% - PECL t f PECL Output Skew VDD OUT 2.0V 50% OUT PECL Transistion Time Waveform DUTY CYCLE PLL602-11 Preliminary MIN. MAX. V – 1.025 DD V – 1.620 DD MIN. TYP. MAX. 0.6 1.5 0.5 1.5 t SKEW Rev 07/17/01 Page 4 UNITS V V UNITS ...

Page 5

... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 A1 0.65 BSC e 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL602- PLL602-11 Preliminary REVISION CODE (when applicable) TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC, O=TSSOP Rev 07/17/01 Page 5 ...

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