PLL701-01 PhaseLink (PLL), PLL701-01 Datasheet - Page 3

• Manufacturer Part Number: PLL701-01
• Description: , 1x Out, 15-30MHz In, 15-30MHz Out, SST
• Manufacturer: PhaseLink (PLL)

PLL701-01/02/04/06
Preliminary
Low EMI Spread Spectrum Multiplier Clock
Connecting a selection pin to a logical “one”
All selection pins have an internal pull-up resistor (30k
for pins 3, 4, 7, and 120k
for pin 2). This internal pull-up
resistor will pull the input value to a logical “one” (pull-up) by default, i.e. when no resistive load is connected
between the pin and GND. No external pull-up resistor is therefore required for connecting a logical “one” upon
power-up.
Connecting a selection pin to a logical “zero”
For an input only pin, i.e. pins 3 (SC0), 4 (SC1), and 7 (SC2), the pin simply needs to be grounded to pull the input
down to a logical “zero”. Connecting the bi-directional pin (SD) to a logical “zero” will however require the use of an
external loading resistor between the pin and GND that has to be sufficiently small (compared to the internal pull-
up resistor) so that the pin voltage be pulled below 0.8V (logical “zero”). In order to avoid loading effects when the
pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In
general, it is recommended to use an external resistor of around 27k
(see Application Diagram).
APPLICATION DIAGRAM FOR OUTPUT AND MODULATION SELECTION
Internal to chip
External Circuitry
VDD
R
up
R
Power Up
Reset
RB
Clock Load
Pin2 (XOUT/SD)
XIN
EN
27k
SD or
Latch
SC0~SC2
Jumper options
NOTE: Rup=120k
for SD (Pin2); Rup=30k
for SC0~SC2. R starts from 1 to 0 while RB starts from 0 to 1.
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Rev 09/11/02 Page 3