PLL701-05 PhaseLink (PLL), PLL701-05 Datasheet - Page 4

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PLL701-05

Manufacturer Part Number
PLL701-05
Description
Low EMI Spread Spectrum Multiplier IC
Manufacturer
PhaseLink (PLL)
Datasheet
2. DC/AC Specifications
*Note: Pin XIN and XOUT each has a 36pF capacitance. When used with a XTAL, the two capacitors combined load the crystal with 18pF. If driving XIN
with a reference clock signal, the load capacitance will be 36pF (typical).
3. Timing Characteristics
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
Supply Voltage
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Output High Voltage
Output Low Voltage
Input Frequency
Maximum interruption of F
Load Capacitance
Pull-up Resistor
Pull-up Resistor
Short Circuit Current
3.3V Dynamic Supply Current
Cycle to Cycle Jitter
Cycle to Cycle Jitter
Output Duty Cycle
PARAMETERS
PARAMETERS
Rise Time
Fall Time
IN
SYMBOL
T
T
cyc-cyc
cyc-cyc
D
T
T
SYMBOL
r
T
f
F
V
V
V
R
R
V
F
V
I
C
I
I
I
XIN
CC
IH
sc
DD
IL
OH
OL
IH
IN
up
up
IL
L
Measured at 0.8V ~ 2.0V @ 3.3V
Measured at 2.0V ~ 0.8V @ 3.3V
X1, X2, X4, X8 FOUT @ 3.3V
X3, X5, X6, X7 FOUT @ 3.3V
When using reference clock
When using reference clock
PIN 3,4,5,6,7,8,11,12,14
Between Pin XIN and
When using a crystal
I
I
OH
OL
CONDITIONS
CONDITIONS
=6mA, V
=5mA, V
Low EMI Spread Spectrum Multiplier IC
No Load
XOUT*
PIN 2
DD
DD
=3.3V
=3.3V
See Output Clock Selection table
See Output Clock Selection table
0.7* V
MIN.
2.97
2.4
www.phaselink.com
MIN.
0.78
DD
0.8
45
on page 1
on page 1
TYP.
120
18
30
50
20
TYP.
0.95
0.85
PLL701-50
50
0.3* V
MAX.
Rev 09/20/04 Page 4
3.63
100
100
100
0.4
MAX.
100
150
1.1
0.9
55
DD
UNITS
UNITS
MHz
MHz
kΩ
kΩ
mA
mA
µA
µA
µs
pF
V
V
V
ns
ns
ps
ps
%

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