NTB52N10T4 ONSEMI [ON Semiconductor], NTB52N10T4 Datasheet

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NTB52N10T4

Manufacturer Part Number
NTB52N10T4
Description
N-Channel Enhancement−Mode D2PAK
Manufacturer
ONSEMI [ON Semiconductor]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NTB52N10T4
Manufacturer:
ON SEMICONDUCTOR
Quantity:
30 000
NTB52N10
Power MOSFET
52 Amps, 100 Volts
N−Channel Enhancement−Mode D
Features
Typical Applications
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%.
2. When surface mounted to an FR4 board using the minimum recommended
MAXIMUM RATINGS
© Semiconductor Components Industries, LLC, 2005
August, 2005 − Rev. 3
Drain−to−Source Voltage
Drain−to−Source Voltage (R
Gate−to−Source Voltage
Drain Current
Total Power Dissipation @ T
Derate above 25°C
Total Power Dissipation @ T
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
(V
I
Thermal Resistance
Maximum Lead Temperature for Soldering
Purposes, 1/8in from case for 10 seconds
L(pk)
Fast Recovery Diode
Source−to−Drain Diode Recovery Time Comparable to a Discrete
Avalanche Energy Specified
I
Mounting Information Provided for the D
Pb−Free Packages are Available
PWM Motor Controls
Power Supplies
Converters
pad size, (Cu. Area 0.412 in
DD
DSS
= 40 A, L = 1.0 mH, R
= 50 Vdc, V
and R
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 2)
DS(on)
− Continuous
− Non−Repetitive (t
− Continuous @ T
− Continuous @ T
− Pulsed (Note 1)
GS
Rating
J
= 10 Vdc,
Specified at Elevated Temperature
= 25°C
(T
J
= 25°C unless otherwise noted)
G
GS
A
A
= 25 W)
2
= 25°C
= 25°C (Note 2)
).
= 1.0 MW)
A
A
p
= 25°C
= 100°C
v10 ms)
2
PAK Package
Symbol
T
V
V
V
R
R
R
J
V
E
I
GSM
P
, T
DSS
DGR
T
I
I
DM
qJC
qJA
qJA
GS
AS
D
D
D
L
stg
−55 to
Value
+150
"20
"40
1.43
62.5
100
100
156
178
800
260
2.0
0.7
52
40
50
2
PAK
1
W/°C
°C/W
Unit
Vdc
Vdc
Vdc
Adc
mJ
°C
°C
W
W
NTB52N10
NTB52N10G
NTB52N10T4
NTB52N10T4G
†For information on tape and reel specifications,
1
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Device
CASE 418B
100 V
2
V
STYLE 2
D
DSS
3
2
NTB52N10 = Device Code
A
Y
WW
G
PAK
ORDERING INFORMATION
G
http://onsemi.com
4
30 mW @ 10 V
R
N−Channel
(Pb−Free)
(Pb−Free)
Package
DS(ON)
= Assembly Location
= Year
= Work Week
= Pb−Free Package
D
D
D
D
2
2
2
2
D
PAK
PAK
PAK
PAK
MARKING DIAGRAM
& PIN ASSIGNMENT
Publication Order Number:
Gate
TYP
S
1
NTB
52N10G
AYWW
Drain
Drain
800 / Tape & Reel
800 / Tape & Reel
4
2
50 Units / Rail
50 Units / Rail
Shipping
NTB52N10/D
I
D
3
Source
52 A
MAX

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NTB52N10T4 Summary of contents

Page 1

... Device R 62.5 qJA NTB52N10 50 R qJA NTB52N10G °C T 260 L NTB52N10T4 NTB52N10T4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 1 http://onsemi.com R TYP I MAX DSS DS(ON N− ...

Page 2

ELECTRICAL CHARACTERISTICS Characteristic OFF CHARACTERISTICS Drain−to−Source Breakdown Voltage = 250 mAdc Vdc Temperature Coefficient (Positive) Zero Gate Voltage Drain Current ( Vdc 100 Vdc 25° ...

Page 3

25° DRAIN−TO−SOURCE VOLTAGE (VOLTS) DS Figure ...

Page 4

Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the ...

Page 5

TOTAL GATE CHARGE (nC) G Figure 8. Gate−To−Source and Drain−To−Source Voltage versus Total Charge ...

Page 6

SINGLE PULSE T = 25°C C 100 LIMIT DS(on) THERMAL LIMIT PACKAGE LIMIT 0.1 0 DRAIN−TO−SOURCE VOLTAGE (VOLTS) DS Figure 11. Maximum Rated Forward Biased Safe Operating ...

Page 7

−T− SEATING PLANE 0.13 (0.005 VARIABLE CONFIGURATION ZONE VIEW W−W VIEW W−W 1 10.66 0.42 *For additional information on our Pb−Free strategy ...

Page 8

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for ...

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