h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 25

• Manufacturer Part Number: h8s-2111b
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Figure 10.13 Timing of Input Capture Signal
Figure 10.14 Conflict between TCNT Write and Clear.............................................................. 216
Figure 10.15 Conflict between TCNT Write and Count-Up....................................................... 216
Figure 10.16 Conflict between TCOR Write and Compare-Match ............................................ 217
Section 11 Watchdog Timer (WDT)
Figure 11.1 Block Diagram of WDT .......................................................................................... 222
Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation................................................. 228
Figure 11.3 Interval Timer Mode Operation............................................................................... 229
Figure 11.4 OVF Flag Set Timing .............................................................................................. 229
Figure 11.5 Output Timing of RESO signal ............................................................................... 230
Figure 11.6 Writing to TCNT and TCSR (WDT_0)................................................................... 231
Figure 11.7 Conflict between TCNT Write and Increment ........................................................ 232
Figure 11.8 Sample Circuit for Resetting System by RESO Signal ........................................... 233
Section 12 Serial Communication Interface (SCI)
Figure 12.1 Block Diagram of SCI............................................................................................. 236
Figure 12.2 Data Format in Asynchronous Communication
Figure 12.3 Receive Data Sampling Timing in Asynchronous Mode ........................................ 251
Figure 12.4 Relation between Output Clock and Transmit Data Phase
Figure 12.5 Sample SCI Initialization Flowchart ....................................................................... 253
Figure 12.6 Example of SCI Transmit Operation in Asynchronous Mode
Figure 12.7 Sample Serial Transmission Flowchart ................................................................... 255
Figure 12.8 Example of SCI Receive Operation in Asynchronous Mode
Figure 12.9 Sample Serial Reception Flowchart (1)................................................................... 257
Figure 12.9 Sample Serial Reception Flowchart (2)................................................................... 258
Figure 12.10 Example of Communication Using Multiprocessor Format
Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart ........................................ 260
Figure 12.12 Example of SCI Receive Operation
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (1)........................................ 262
Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2)........................................ 263
Figure 12.14 Data Format in Clocked Synchronous Communication (LSB-First)..................... 264
Figure 12.15 Sample SCI Initialization Flowchart ..................................................................... 265
Figure 12.16 Example of SCI Transmit Operation in Clocked Synchronous Mode................... 266
Figure 12.17 Sample Serial Transmission Flowchart ................................................................. 267
Figure 12.18 Example of SCI Receive Operation in Clocked Synchronous Mode .................... 268
Figure 12.19 Sample Serial Reception Flowchart ...................................................................... 269
(Example with 8-Bit Data, Parity, Two Stop Bits) ................................................. 249
(Asynchronous Mode) ............................................................................................ 252
(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 254
(Example with 8-Bit Data, Parity, One Stop Bit).................................................... 256
(Input capture signal is input during TICRR and TICRF read) ............................. 213
(Transmission of Data H'AA to Receiving Station A).......................................... 259
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................. 261
Rev. 1.00, 05/04, page xxv of xxxiv