h8s-2111b Renesas Electronics Corporation., h8s-2111b Datasheet - Page 383
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h8s-2111b
Manufacturer Part Number
h8s-2111b
Description
Renesas 16-bit Single-chip Microcomputer H8s Family / H8s/2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2111B.pdf
(582 pages)
- Current page: 383 of 582
- Download datasheet (4Mb)
This LSI has three on-chip keyboard buffer controller channels. The keyboard buffer controller is
provided with functions conforming to the PS/2 interface specifications.
Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line
(KCLK), providing economical use of connectors, board surface area, etc. Figure 14.1 shows a
block diagram of the keyboard buffer controller.
14.1
• Conforms to PS/2 interface specifications
• Direct bus drive (via the KCLK and KD pins)
• Interrupt sources: on completion of data reception and on detection of clock edge
• Error detection: parity error and stop bit monitoring
IFKEY10A_000020020700
[Legend]
KD:
KCLK:
KBBR:
KBCRH:
KBCRL:
KD
(PS2AD,
PS2BD,
PS2CD)
KCLK
(PS2AC,
PS2BC,
PS2CC)
Features
KBC data I/O pin
KBC clock I/O pin
Keyboard data buffer register
Keyboard control register H
Keyboard control register L
Section 14 Keyboard Buffer Controller
Figure 14.1 Block Diagram of Keyboard Buffer Controller
Control
logic
KDI
KCLKI
Parity
KDO
KCLKO
Register counter value
KBI interrupt
KBCRH
KBCRL
KBBR
Rev. 1.00, 05/04, page 349 of 544
Internal
data bus
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