h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 161

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
4
3
2
1
0
Bit Name
ASTCP
ADFULLE
EXCKS
BUSDIVE
CPCSE
Initial Value
1
0
0
1
0
R/W
R/W
R/W
R/W
R/W
R/W
Selects the number of states for access to the CP/CF
expansion area when the CPCSE bit in BCR2 is set to
1. This bit also enables or disables wait-state insertion.
0: 2-state access space. Wait state insertion disabled in
1: 3-state access space. Wait state insertion enabled in
Address Output Full Enable
Controls the IOS signal output and address output in
access to the 256-kbyte expansion area and CP/CF
expansion area. For details, refer to section 9, I/O Ports.
Selects the operating clock used in external expansion
area access.
0: Medium-speed clock is selected as the operating
1: System clock ( ) is selected as the operating clock.
The operating clock is switched in the bus cycle prior to
external expansion area access.
Controls the bus arbitration timing for the divided bus
cycles in the RFU operation. For details, refer to section
8, RAM FIFO Unit (RFU).
Selects the expansion area to be accessed.
0: External address space (basic expansion area)
1: CP/CF expansion area (basic mode when CFE bit in
Description
CP/CF Expansion Area Access State Control
External Expansion Clock Select
Bus Division Arbitration Enable
CP/CF Expansion Area Enable
CP/CF expansion area access
CP/CF expansion area access
clock
BCR is 0, memory card mode when CFE bit in BCR
is 1)
Rev. 3.00 Jan 25, 2006 page 109 of 872
Section 6 Bus Controller
REJ09B0286-0300