h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 222

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 8 RAM-FIFO Unit (RFU)
8.2.2
BAR is a 16-bit register provided in each pointer set, and allocated to bits 19 to 4 in FSTR. The
base address should be set at the boundary specified by the BUD2 to BUD0 bits in DTCRA.
Otherwise, address specification by the pointer and status display by calculation inter-pointers
may not be performed correctly.
8.2.3
RAR is an 11-bit pointer provided in each pointer set, and allocated to bits 10 to 0 in FSTR.
Rev. 3.00 Jan 25, 2006 page 170 of 872
REJ09B0286-0300
Bit
31
to
20
19
to
4
3
to
0
Bit
31
to
11
10
to
0
Bit Name
—
BA19
to
BA4
—
Bit Name
—
RA10
to
RA0
Base Address Register (BAR)
Read Address Pointer (RAR)
Initial Value
All 1
Undefined
All 0
Initial Value
All 0
All 0
R/W
R
R/W
R
R/W
R
R/W
Description
Base Addresses 31 to 20
These bits are always read as 1 and cannot be
modified.
Base Addresses 19 to 4
These bits specify a RAM base address that
can be used as the FIFO.
Base Addresses 3 to 0
These bits are always read as 0 and cannot be
modified.
Description
Read Addresses 31 to 11
These bits are always read as 0 and cannot be
modified.
Read Addresses 10 to 0
These bits are pointers to specify the RAM
address to be read from in a RAM read cycle of
the RFU. The RAM address is calculated by
BAR + RAR. These can be read as NRA. These
bits are incremented for the number of bytes to
be read for each RAM read cycle. However,
these bits are not incremented and cleared to 0
when exceeding the selected FIFO size.