h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 328

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 11 14-Bit PWM Timer (PWMX)
11.3.2
DADRA corresponds to PWM (D/A) channel A, and DADRB to PWM (D/A) channel B. The
DADR registers cannot be accessed in 8-bit units. The DADR registers should always be accessed
in 16-bit units. For details, see section 11.4, Bus Master Interface.
DADRA
Rev. 3.00 Jan 25, 2006 page 276 of 872
REJ09B0286-0300
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit Name
DA13
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
CFS
—
PWM (D/A) Data Registers A and B (DADRA and DADRB)
Initial Value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
D/A Data 13 to 0
These bits set a digital value to be converted to an
analog value.
In each base cycle, the DACNT value is continually
compared with the DADR value to determine the duty
cycle of the output waveform, and to decide whether to
output a fine-adjustment pulse equal in width to the
resolution. To enable this operation, this register must
be set within a range that depends on the CFS bit. If the
DADR value is outside this range, the PWM output is
held constant.
A channel can be operated with 12-bit precision by
keeping the two lowest data bits (DA1 and DA0) cleared
to 0. The two lowest data bits correspond to the two
highest bits in DACNT.
Carrier Frequency Select
0: Base cycle = resolution (T)
1: Base cycle = resolution (T)
Reserved
This bit is always read as 1 and cannot be modified.
DADR range = H'0401 to H'FFFD
DADR range = H'0103 to H'FFFF
64
256