h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 509

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

The high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) × bit rate or
(3/16 × bit rate) +1.08 s at maximum. For example, when the frequency of system clock is 20
MHz, a high-level pulse width of at least 1.4 µs to 1.6 µs can be specified.
For serial data of level 1, no pulses are output.
Reception: During reception, IR frames are converted to UART frames using the IrDA interface
before inputting to SCI_1.
Data of level 0 is output each time a high-level pulse is detected and data of level 1 is output when
no pulse is detected in a bit cycle. If a pulse has a high-level width of less than 1.41 s, the
minimum width allowed, the pulse is recognized as level 0.
High-Level Pulse Width Selection: Table 16.12 shows possible settings for bits IrCKS2 to
IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the
pulse width shorter than 3/16 times the bit rate in transmission.
Transmission
Start
bit
Start
bit
Bit
cycle
Figure 16.37 IrDA Transmission and Reception
0
0
1
1
Section 16 Serial Communication Interface (SCI, IrDA, and CRC)
0
0
UART frame
IR frame
1
1
0
0
Data
Data
0
0
Rev. 3.00 Jan 25, 2006 page 457 of 872
Reception
1
1
Pulse width is 1.6 µs to
3/16 bit cycle
1
1
0
0
Stop
bit
Stop
bit
1
1
REJ09B0286-0300