h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 571

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

17.5.3
The data buffer of the IIC module can receive data consecutively since it consists of ICDRR and
ICDRS. However, if the completion of receiving the last data is delayed, there will be a conflict
between the instruction to issue a stop condition and the SCl clock output to receive the next data.
This may generate unnecessary clocks or fix the output level of the SDA line as low.
The switch timing of the ACKB bit in ICSR should be controlled because the acknowledge bit
does not return an acknowledge signal after receiving the last data in master mode.
These problems can be avoided by using the WAIT function. Follow the procedure shown below.
In I
and returns an acknowledge signal. The slave device transmits data. The reception procedure and
operations for sequential data reception with the wait function in synchronization with the ICDR
read operation are shown below.
(master output)
(master output)
(slave output)
User processing
Note: * Data write timing in ICDR
2
Incorrect
operation
C bus format master receive mode, the master device outputs the receive clock, receives data,
SDA
SCL
SDA
ICDR
IRTR
IRIC
Start condition generation
*
Master Receive Operation
[4] BBSY set to 1
Figure 17.7 Master Transmit Mode Operation Timing Example
SCP cleared to 0
(start condition
issuance)
[5]
Normal
operation
[6] ICDR write
Bit 7
1
Address + R/W
Bit 6
(MLS = WAIT = 0)
2
Bit 5
[6] IRIC clear
3
Slave address
Bit 4
4
Bit 3
5
Rev. 3.00 Jan 25, 2006 page 519 of 872
Bit 2
6
Bit 1
7
Section 17 I
R/W
Bit 0
8
[7]
9
A
2
C Bus Interface (IIC)
REJ09B0286-0300
[9] ICDR write
[9] IRIC clear
Bit 7
Data 1
1
Data 1
Bit 6
2