h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 786

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

Section 24 ROM
Rev. 3.00 Jan 25, 2006 page 734 of 872
REJ09B0286-0300
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written
Reprogram Data Computation Table
2. Verify data is read in 16-bit (word) units.
3. Even bits for which programming has been completed will be subjected to programming
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
5. A write pulse of z1 s or z2 s is applied according to the progress of the programming operation. See Note7 for details of the pulse widths. When writing of
6. The values of x, y, z1, z2, z3, , , , , , , and N are shown in section 29.6, Flash Memory Characteristics.
Original Data
to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing
fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
once again if the result of the subsequent verify operation is NG.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
additional-programming data is executed, a z3 s write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
Note 7: Write Pulse Width
(D)
Note: Use a z3 s write pulse for additional programming.
0
0
1
1
Number of Writes n
Write pulse application subroutine
Wait (z1) s, (z2) s or (z3) s
Clear PSU bit in FLMCR2
1000
Sub-Routine Write Pulse
Set PSU bit in FLMCR2
998
999
Verify Data
Clear P bit in FLMCR1
10
11
12
13
1
2
3
4
5
6
7
8
9
Set P bit in FLMCR1
Reprogram data storage
Additional-programming
Program data storage
(V)
0
1
0
1
Disable WDT
WDT enable
data storage area
Wait (α) s
Wait (γ) s
Wait (β) s
area (128 bytes)
area (128 bytes)
End Sub
(128 bytes)
RAM
Reprogram Data
Write Time (z) s
*
6
(X)
1
0
1
1
Figure 24.9 Program/Program-Verify Flowchart
z1
z1
z1
z1
z1
z1
z2
z2
z2
z2
z2
z2
z2
z2
z2
z2
Programming completed
Programming incomplete; reprogram
Still in erased state; no action
*
*
*
*
5
6
6
6
*
6
Comments
Increment address
Successively write 128-byte data from additional-
Apply write pulse (Additional programming) z3 s
Additional-Programming Data Computation Table
programming data area in RAM to flash memory
Transfer reprogram data to reprogram data area
Reprogram Data
NG
Additional-programming data computation
Store 128-byte program data in program
data area consecutively to flash memory
Transfer additional-programming data to
Write 128-byte data in RAM reprogram
H'FF dummy write to verify address
data area and reprogram data area
(X')
additional-programming data area
Apply write pulse z1 s or z2 s
0
0
1
1
Reprogram data computation
data verification completed?
Clear SWE bit in FLMCR1
Set SWE bit in FLMCR1
Clear PV bit in FLMCR1
Set PV bit in FLMCR1
Start of programming
End of programming
Read verify data
Write data =
verify data?
OK
Wait (η) s
OK
Wait (x) s
Wait (γ) s
Wait (ε) s
Wait (θ) s
Verify Data
128-byte
OK
START
m = 0 ?
m = 0
6
6
n = 1
(V)
0
1
0
1
n ?
n?
OK
OK
Sub-Routine-Call
Programming Data (Y)
Additional-
NG
NG
NG
0
1
1
1
*
NG
6
*
*
*
*
*
*
*
6
4
1
6
6
6
2
*
*
*
*
*
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
m = 1
*
4
3
4
6
See Note 7 for pulse width
1
3
Clear SWE bit in FLMCR1
Additional programming to be executed
Additional programming not to be executed
Additional programming not to be executed
Programming failure
s
Wait (θ) s
n
(N)?
OK
*
Comments
6
NG
n
n + 1
*
6