h8s-2158 Renesas Electronics Corporation., h8s-2158 Datasheet - Page 809

• Manufacturer Part Number: h8s-2158
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family/h8s/2100 Series
• Manufacturer: Renesas Electronics Corporation.

25.5.2
1. Boundary scan mode does not cover power-supply-related pins (VCC, VCL, VSS,
2. Boundary scan mode covers clock-related pins (EXTAL, XTAL, X1, and X2).
3. Boundary scan mode does not cover reset- and standby-related pins (RES, STBY, and RESO).
4. Boundary scan mode does not cover H-UDI-related pins (ETCK, ETDI, ETDO, ETMS, and
5. Fix the MD2 pin high.
Data loaded into the output pin boundary scan register in the Capture-DR state is not used for
external circuit testing (it is replaced by a shift operation).
CLAMP [Instruction code: B'0010]
When the CLAMP instruction is enabled, the output pin outputs the value of the boundary scan
register that has been previously set by the SAMPLE/PRELOAD instruction. While the
CLAMP instruction is enabled, the state of the boundary scan register maintains the previous
state regardless of the state of the TAP controller.
A bypass register is connected between the ETDI and ETDO pins. The related circuit operates
in the same way when the BYPASS instruction is enabled.
HIGHZ [Instruction code: B'0011]
When the HIGHZ instruction is enabled, all output pins enter a high-impedance state. While
the HIGHZ instruction is enabled, the state of the boundary scan register maintains the
previous state regardless of the state of the TAP controller.
A bypass register is connected between the ETDI and ETDO pins. The related circuit operates
in the same way when the BYPASS instruction is enabled.
IDCODE [Instruction code: B'1110]
When the IDCODE instruction is enabled, the value of the ID code register is output from the
ETDO pin with LSB first when the TAP controller is in the Shift-DR state. While the
IDCODE instruction is being executed, the test circuit does not affect the system circuit.
When the TAP controller is in the Test-Logic-Reset state, the instruction register is initialized
to the IDCODE instruction.
AVCC/DrVCC, AVSS/DrVSS, and AVref).
ETRST).
Notes
Section 25 User Debug Interface (H-UDI)
Rev. 3.00 Jan 25, 2006 page 757 of 872
REJ09B0286-0300