h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 101
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h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 101 of 570
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5.4
5.4.1
There are two external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore
this LSI from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
• The interrupt exception handling for interrupt requests IRQ7 to IRQ0 can be started at an
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
The detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been
set for input or output. However, when a pin is used as an external interrupt input pin, do not clear
the corresponding port DDR to 0 to use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.
independent vector address.
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
by software.
Interrupt Sources
External Interrupts
input
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0
n = 7 to 0
IRQnSCA, IRQnSCB
detection circuit
Edge/level
Clear signal
S
R
IRQnF
Q
IRQnE
Rev. 2.00, 03/04, page 69 of 534
IRQn interrupt
request
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