h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 127

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

Bit
6
5
4, 3
Bit Name
RCDM
DDS

Initial
Value
0
0
All 0
R/W
R/W
R/W
R/W
RAS Down Mode
When access to DRAM space is interrupted by an
access to normal space, an access to an internal I/O
register, etc., this bit selects whether the RAS signal is
held low while waiting for the next DRAM access (RAS
down mode), or is driven high again (RAS up mode).
The setting of this bit is valid only when the BE bit is set
to 1.
If this bit is cleared to 0 when set to 1 in the RAS down
state, the RAS down state is cleared at that point, and
RAS goes high.
When using DRAM interface in RAS down mode and
RAS down state is not continued, a 1-state idle cycle is
inserted to drive RAS signal high.
0: RAS up mode selected for DRAM space access
1: RAS down mode selected for DRAM space access
Reserved
Description
DMAC Single Address Transfer Option
Selects whether full access is always performed or
burst access is enabled when DMAC single address
transfer is performed on the DRAM interface.
When the BE bit is cleared to 0 in DRAMCR, disabling
DRAM burst access, DMAC single address transfer is
performed in full access mode regardless of the setting
of this bit.
This bit has no effect on other bus master external
accesses or DMAC dual address transfers. If this bit is
set to 1, the DACK output timing is changed.
0: Full access is always executed
1: Burst access is enabled
These bits can be read from or written to. However, the
write value should always be 0.
Rev. 2.00, 03/04, page 95 of 534