h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 161
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h8s-2172
Manufacturer Part Number
h8s-2172
Description
Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.H8S-2172.pdf
(570 pages)
- Current page: 161 of 570
- Download datasheet (5Mb)
6.6.9
When inserting wait states in a DRAM access cycle, program wait insertion is specified.
Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and
to extend the write data setup time relative to the falling edge of CAS in a write access.
When the AST2 bit in ACSCR is set to 1, from 0 to 7 wait states can be inserted automatically
between the T
Figures 6.27 and 6.28 show examples of wait cycle insertion timing in the case of 2-state and 3-
state column address output cycles.
Figure 6.27 Example of Wait State Insertion Timing (2-State Column Address Output)
Read
Write
Wait Control
c1
state and T
φ
Address bus
Data bus
Data bus
(
(
(
(
,
,
)
)
)
)
c2
state, according to the settings of WTCR.
T
Row address
p
T
r
High
High
T
c1
Column address
T
w
Rev. 2.00, 03/04, page 129 of 534
T
w
T
c2
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