h8s-2172 Renesas Electronics Corporation., h8s-2172 Datasheet - Page 164

• Manufacturer Part Number: h8s-2172
• Description: Renesas 16-bit Single-chip Microcomputer H8s Family H8s-2100 Series
• Manufacturer: Renesas Electronics Corporation.

6.6.11
With DRAM, in addition to full access (normal access) in which data is accessed by outputting a
row address for each access, a fast page mode is also provided which can be used when making
consecutive accesses to the same row address. This mode enables fast (burst) access of data by
simply changing the column address after the row address has been output. Burst access can be
selected by setting the BE bit to 1 in DRAMCR.
Burst Access (Fast Page Mode): Figures 6.31 and 6.32 show the operation timing for burst
access. When there are consecutive access cycles for DRAM space, the CAS signal and column
address output cycles (two states) continue as long as the row address is the same for consecutive
access cycles. The row address used for the comparison is set with bits MXC2 to MXC0 in
DRAMCR.
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details, see section 6.6.9, Wait Control.
Rev. 2.00, 03/04, page 132 of 534
Burst Operation
(Address shift size
set to 11 bits)
This LSI
Figure 6.30 Example of 2-CAS DRAM Connection
RAS (CS2)
D15 to D0
RD (OE)
UCAS
LCAS
A12
A11
A10
WE
A9
A8
A7
A6
A5
A4
A3
A2
A1
8-Mbyte × 16-bit configuration
RAS
UCAS
LCAS
WE
OE
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
D15 to D0
2-CAS type 128-Mbit DRAM
11-bit column address
Row address input:
A11 to A0
Column address input:
A10 to A0